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rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a ADUC816 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 world wide web site: http://www.analog.com fax: 781/326-8703 ? analog devices, inc., 2001 microconverter , dual-channel 16-bit adcs with embedded flash mcu functional block diagram 8 kbytes flash/ee program memory 640 bytes flash/ee data memory 256 bytes user ram 3 16 bit timer/counters 1 time interval counter 4 parallel ports 8051-based mcu with additional peripherals on-chip monitors power supply monitor watchdog timer i 2 c-compatible uart and spi serial i/o pga ADUC816 prog. clock divider xtal2xtal1 buf avdd agnd mux temp sensor refin+ refin external vref detect internal bandgap vref ain1 ain2 ain3 ain4 ain5 auxiliary 16-bit - adc primary 16-bit - adc mux osc & pll 12-bit voltage o/p dac buf current source mux avdd iexc1 iexc2 dac features high-resolution sigma-delta adcs dual 16-bit independent adcs programmable gain front end 16-bit no missing codes, primary adc 13-bit p-p resolution @ 20 hz, 20 mv range 16-bit p-p resolution @ 20 hz, 2.56 v range memory 8 kbytes on-chip flash/ee program memory 640 bytes on-chip flash/ee data memory flash/ee, 100 year retention, 100 kcycles endurance 256 bytes on-chip data ram 8051-based core 8051-compatible instruction set (12.58 mhz max) 32 khz external crystal, on-chip programmable pll three 16-bit timer/counters 26 programmable i/o lines 11 interrupt sources, two priority levels power specified for 3 v and 5 v operation normal: 3 ma @ 3 v (core clk = 1.5 mhz) power-down: 20 a (32 khz crystal running) on-chip peripherals on-chip temperature sensor 12-bit voltage output dac dual excitation current sources reference detect circuit time interval counter (tic) uart serial i/o i 2 c ? -compatible and spi ? serial i/o watchdog timer (wdt), power supply monitor (psm) applications intelligent sensors (ieee1451.2-compatible) weigh scales portable instrumentation pressure transducers 4C20 ma transmitters microconverter is a registered trademark of analog devices, inc. spi is a registered trademark of motorola, inc. i 2 c is a registered trademark of philips semiconductors, inc. general description the ADUC816 is a complete smart transducer front-end, inte- grating two high-resolution sigma-delta adcs, an 8-bit mcu, and program/data flash/ee mem ory on a single chip. this low power device accepts low-level signals directly from a transducer. the two independent adcs (primary and auxiliary) include a temperature sensor and a pga (allowing direct measurement of low-level signals). the adcs with on-chip digital filtering are intended for the measurement of wide dynamic range, low frequency signals, such as those in weigh sc ale, strain gauge, pressure transducer, or temperature measurement applications. the adc output data rates are programmable and the adc output resolution will vary with the programmed gain and output rate. the device operates from a 32 khz crystal with an on-chip pll generating a high-frequency clock of 12.58 mhz. this clock is, in turn, routed through a programmable clock divider from which the mcu core clock operating frequency is generated. the microcontroller core is an 8052 and therefore 8051-instruction- set-compatible. the microcontroller core machine cycle consists of 12 core clock periods of the selected core operating frequency. 8 kbytes of nonvolatile flash/ee program memory are provided on-chip. 640 bytes of nonvolatile flash/ee data memory and 256 bytes ram are also integrated on-chip. the ADUC816 also incorporates additional analog functionality with a 12-bit dac, current sources, power supply monitor, and a bandgap reference. on-chip digital peripherals include a watchdog timer, time interval counter, three timers/counters, and three serial i/o ports (spi, uart, and i 2 c-compatible). on-chip factory firmware supports in-circuit serial download and debug modes (via uart), as well as single-pin emulation mode via the ea pin. a functional block diagram of the ADUC816 is shown above with a more detailed block diagram shown in figure 12. the part operates from a single 3 v or 5 v supply. when operating from 3 v supplies, the power dissipation for the part is below 10 mw. the ADUC816 is housed in a 52-lead mqfp package.
rev. 0 ADUC816 C2C features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 timing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . 18 ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 pin function descriptions . . . . . . . . . . . . . . . . . . . . . . 19 ADUC816 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 21 memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 overview of mcu-related sfrs . . . . . . . . . . . . . . . . . . 23 accumulator sfr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 b sfr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 stack pointer sfr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 data pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 program status word sfr . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 power control sfr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 special function registers . . . . . . . . . . . . . . . . . . . . . 24 sfr interface to the primary and auxiliary adcs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 adcstat (adc status register) . . . . . . . . . . . . . . . . . . . . . . 25 adcmode (adc mode register) . . . . . . . . . . . . . . . . . . . . . 26 adc0con (primary adc control register) . . . . . . . . . . . . . . 27 adc1con (auxiliary adc control register) . . . . . . . . . . . . . 28 sf (sinc filter register) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 icon (current sources control register) . . . . . . . . . . . . . . . . 29 adc0h/adc0m (primary adc conversion result registers) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 adc1h/adc1l (auxiliary adc conversion result registers) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 of0h/of0m (primary adc offset calibration registers) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 of1h/of1l (auxiliary adc offset calibration registers) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 gn0h/gn0m (primary adc gain calibration registers) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 gn1h/gn1l (auxiliary adc gain calibration registers) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 primary and auxiliary adc circuit description overview . . . . . . . . . . . . . . . . . . . . . . . . . . 31 primary adc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 auxiliary adc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 primary and auxiliary adc noise performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 analog input channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 primary and auxiliary adc inputs . . . . . . . . . . . . . . . . . . . . . . 33 analog input ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 programmable gain amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . 34 bipolar/unipolar inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 burnout currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 excitation currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 reference input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 reference detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 sigma-delta modulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 digital filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 adc chopping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 nonvolatile flash/ee memory . . . . . . . . . . . . . . . . . . 37 flash/ee memory overview . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 flash/ee memory and the ADUC816 . . . . . . . . . . . . . . . . . . . . 37 ADUC816 flash/ee memory reliability . . . . . . . . . . . . . . . . . . 37 using the flash/ee program memory . . . . . . . . . . . . . . . . . . . . 38 flash/ee program memory security . . . . . . . . . . . . . . . . . . . . . 38 using the flash/ee data memory . . . . . . . . . . . . . . . . . . . . . . . 39 econ?lash/ee memory control sfr . . . . . . . . . . . . . . . . . . 39 flash/ee memory timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 using the flash/ee memory interface . . . . . . . . . . . . . . . . . . . . 40 erase-all . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 program a byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 user interface to other on-chip ADUC816 peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 dac . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 on-chip pll . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 time interval counter (tic) . . . . . . . . . . . . . . . . . . . . . . . . . . 43 watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 power supply monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 serial peripheral interface . . . . . . . . . . . . . . . . . . . . . 48 miso (master in, slave out data i/o pin), pin 14 . . . . . . . . . 48 mosi (master out, slave in pin), pin 27 . . . . . . . . . . . . . . . . . 48 sclock (serial clock i/o pin), pin 26 . . . . . . . . . . . . . . . . . . 48 ss (slave select input pin), pin 13 . . . . . . . . . . . . . . . . . . . . . . 48 using the spi interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 spi interface?aster mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 spi interface?lave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 i 2 c-compatible interface . . . . . . . . . . . . . . . . . . . . . . . . 50 8051-compatible on-chip peripherals . . . . . . . . . . . . 51 parallel i/o ports 0? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 timers/counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 timer/counter 0 and 1 operating modes . . . . . . . . 54 mode 0 (13-bit timer/counter) . . . . . . . . . . . . . . . . . . . . . . . . 54 mode 1 (16-bit timer/counter) . . . . . . . . . . . . . . . . . . . . . . . . 54 mode 2 (8-bit timer/counter with autoreload) . . . . . . . . . . . . 54 mode 3 (two 8-bit timer/counters) . . . . . . . . . . . . . . . . . . . . 54 timer/counter 2 data registers . . . . . . . . . . . . . . . . . . . . . . . . 55 th2 and tl2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 rcap2h and rcap2l . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 timer/counter 2 operating modes . . . . . . . . . . . . . . . . . . . . . . 56 16-bit autoreload mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 16-bit capture mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 uart serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 sbuf . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 mode 0: 8-bit shift register mode . . . . . . . . . . . . . . . . . . . . . . 58 mode 1: 8-bit uart, variable baud rate . . . . . . . . . . . . . . . . 58 mode 2: 9-bit uart with fixed baud rate . . . . . . . . . . . . . . . 58 mode 3: 9-bit uart with variable baud rate . . . . . . . . . . . . . 58 uart serial port baud rate generation . . . . . . . . . . . . . . . . . 58 timer 1 generated baud rates . . . . . . . . . . . . . . . . . . . . . . . . . 59 timer 2 generated baud rates . . . . . . . . . . . . . . . . . . . . . . . . . 59 interrupt system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 interrupt priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 ADUC816 hardware design considerations . . . . . . 62 clock oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 external memory interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 power-on reset operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 power supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 power consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 power-saving modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 grounding and board layout recommendations . . . . . . . . . . . 64 ADUC816 system self-identification . . . . . . . . . . . . . . . . . . . . . 65 other hardware considerations . . . . . . . . . . . . . . . 65 in-circuit serial download access . . . . . . . . . . . . . . . . . . . . . . 65 embedded serial port debugger . . . . . . . . . . . . . . . . . . . . . . . . 65 single-pin emulation mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 enhanced-hooks emulation mode . . . . . . . . . . . . . . . . . . . . . . 66 typical system configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 66 quickstart development system . . . . . . . . . . . . . . . 67 download?n-circuit serial downloader . . . . . . . . . . . . . . . . . 67 debug?n-circuit debugger . . . . . . . . . . . . . . . . . . . . . . . . . . 67 adsim?indows simulator . . . . . . . . . . . . . . . . . . . . . . . . . . 67 outline dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 table of contents
rev. 0 C3C ADUC816 parameter ADUC816bs unit test conditions/comments adc specifications conversion rate 5.4 hz min on both channels 105 hz max programmable in 0.732 ms increments primary adc no missing codes 2 16 bits min 20 hz update rate resolution 13 bits p-p typ range = 20 mv, 20 hz update rate 16 bits p-p typ range = 2.56 v, 20 hz update rate p-p resolution at this range/update rate setting is limited only by the number of bits available from adc output noise see table ix and x output noise varies with selected in adc description update rate and gain range integral nonlinearity 1 lsb max offset error 3 v typ offset error drift 10 nv/ c typ full-scale error 3 10 v typ range = 20 mv to 640 mv 0.5 lsb typ range = 1.28 v to 2.56 v gain error drift 4 0.5 ppm/ c typ adc range matching 0.5 lsb typ ain = 18 mv power supply rejection (psr) 95 dbs typ ain = 7.8 mv, range = 20 mv 80 dbs typ ain = 1 v, range = 2.56 v common-mode dc rejection on ain 95 dbs typ at dc, ain = 7.8 mv, range = 20 mv 90 dbs typ at dc, ain = 1 v, range = 2.56 v on refin 90 dbs typ at dc, ain = 1 v, range = 2.56 v common-mode 50 hz/60 hz rejection 2 20 hz update rate on ain 95 dbs typ 50 hz/60 hz 1 hz, ain = 7.8 mv, range = 20 mv 90 dbs typ 50 hz/60 hz 1 hz, ain = 1 v, range = 2.56 v on refin 90 dbs typ 50 hz/60 hz 1 hz, ain = 1 v, range = 2.56 v normal mode 50 hz/60 hz rejection 2 on ain 60 dbs typ 50 hz/60 hz 1 hz, 20 hz update rate on refin 60 dbs typ 50 hz/60 hz 1 hz, 20 hz update rate auxiliary adc no missing codes 2 16 bits min resolution 16 bits p-p typ range = 2.5 v, 20 hz update rate output noise see table xi output noise varies with selected in adc description update rate integral nonlinearity 1 lsb max offset error ? lsb typ offset error drift 1 v/ c typ full-scale error 5 ?.5 lsb typ gain error drift 4 0.5 ppm/ c typ power supply rejection (psr) 80 dbs typ ain = 1 v, 20 hz update rate normal mode 50 hz/60 hz rejection 2 on ain 60 dbs typ 50 hz/60 hz 1hz on refin 60 dbs typ 50 hz/60 hz 1 hz, 20 hz update rate dac performance dc specifications 6 resolution 12 bits relative accuracy 3 lsb typ differential nonlinearity ? lsb max guaranteed 12-bit monotonic offset error 50 mv max gain error 7 1% maxav dd range 1 % typ v ref range ac specifications 2, 6 voltage output settling time 15 s typ settling time to 1 lsb of final value digital-to-analog glitch energy 10 nvs typ 1 lsb change at major carry (av dd = 2.7 v to 3.6 v or 4.75 v to 5.25 v, dv dd = 2.7 v to 3.6 v or 4.75 v to 5.25 v, refin(+) = 2.5 v; refin(? = agnd; agnd = dgnd = 0 v; xtal1/xtal2 = 32.768 khz crystal; all specifications t min to t max unless otherwise noted.) specifications 1
rev. 0 C4C ADUC816?pecifications 1 parameter ADUC816bs unit test conditions/comments internal reference adc reference reference voltage 1.25 1% v min/max initial tolerance @ 25 c, v dd = 5 v power supply rejection 45 dbs typ reference tempco 100 ppm/ c typ dac reference reference voltage 2.5 1% v min/max initial tolerance @ 25 c, v dd = 5 v power supply rejection 50 dbs typ reference tempco 100 ppm/ c typ analog inputs/reference inputs primary adc differential input voltage ranges 8, 9 external reference voltage = 2.5 v rn2, rn1, rn0 of adc0con set to bipolar mode (adc0con.3 = 0) 20 mv 0 0 0 (unipolar mode 0 mv to 20 mv) 40 mv 0 0 1 (unipolar mode 0 mv to 40 mv) 80 mv 0 1 0 (unipolar mode 0 mv to 80 mv) 160 mv 0 1 1 (unipolar mode 0 mv to 160 mv) 320 mv 1 0 0 (unipolar mode 0 mv to 320 mv) 640 mv 1 0 1 (unipolar mode 0 mv to 640 mv) 1.28 v 1 1 0 (unipolar mode 0 v to 1.28 v) 2.56 v 1 1 1 (unipolar mode 0 v to 2.56 v) analog input current 2 1 na max analog input current drift 5pa/ c typ absolute ain voltage limits agnd + 100 mv v min av dd ?100 mv v max auxiliary adc input voltage range 8, 9 0 to v ref v unipolar mode, for bipolar mode see note 11 average analog input current 125 na/v typ input current will vary with input average analog input current drift 2 2 pa/v/ c typ voltage on the unbuffered auxiliary adc absolute ain voltage limits 10 agnd ?30 mv v min av dd + 30 mv v max external reference inputs refin(+) to refin(? range 2 1v min av dd v max average reference input current 1 a/v typ both adcs enabled average reference input current drift 0.1 na/v/ c typ ?o ext. ref?trigger voltage 0.3 v min noxref bit active if v ref < 0.3 v 0.65 v max noxref bit inactive if v ref > 0.65 v adc system calibration full-scale calibration limit +1.05 fs v max zero-scale calibration limit ?.05 fs v min input span 0.8 fs v min 2.1 fs v max analog (dac) outputs voltage range 0 to v ref v typ dacrn = 0 in daccon sfr 0 to av dd v typ dacrn = 1 in daccon sfr resistive load 10 k ? typ from dac output to agnd capacitive load 100 pf typ from dac output to agnd output impedance 0.5 ? typ i sink 50 a typ temperature sensor accuracy 2 c typ thermal impedance ( ja )90 c/w typ
rev. 0 C5C ADUC816 parameter ADUC816bs unit test conditions/comments transducer burnout current sources ain+ current ?00 na typ ain+ is the selected positive input to the primary adc ain?current +100 na typ ain?is the selected negative input the auxiliary adc initial tolerance @ 25 c drift 10 % typ drift 0.03 %/ c typ excitation current sources output current ?00 a typ available from each current source initial tolerance @ 25 c 10 % typ drift 200 ppm/ c typ initial current matching @ 25 c 1 % typ matching between both current sources drift matching 20 ppm/ c typ line regulation (av dd )1 a/v typ av dd = 5 v + 5% load regulation 0.1 a/v typ output compliance av dd ?0.6 v max agnd min logic inputs all inputs except sclock, reset, and xtal1 v inl , input low voltage 0.8 v max dv dd = 5 v 0.4 v max dv dd = 3 v v inh , input high voltage 2.0 v min sclock and reset only (schmitt-triggered inputs) 2 v t+ 1.3/3 v min/v max dv dd = 5 v 0.95/2.5 v min/v max dv dd = 3 v v t 0.8/1.4 v min/v max dv dd = 5 v 0.4/1.1 v min/v max dv dd = 3 v v t+ ?v t 0.3/0.85 v min/v max dv dd = 5 v 0.3/0.85 v min/v max dv dd = 3 v input currents port 0, p1.2?1.7, ea 10 a max v in = 0 v or v dd sclock, sdata/mosi, miso, ss 11 ?0 min, ?0 max a min/ a max v in = 0 v, dv dd = 5 v, internal pull-up 10 a max v in = v dd , dv dd = 5 v reset 10 a max v in = 0 v, dv dd = 5 v 35 min, 105 max a min/ a max v in = v dd , dv dd = 5 v, internal pull-down p1.0, p1.1, ports 2 and 3 10 a max v in = v dd , dv dd = 5 v ?80 a min v in = 2 v, dv dd = 5 v ?60 a max ?0 a min v in = 450 mv, dv dd = 5 v ?5 a max input capacitance 5 pf typ all digital inputs crystal oscillator (xtal1 and xtal2) logic inputs, xtal1 only v inl , input low voltage 0.8 v max dv dd = 5 v 0.4 v max dv dd = 3 v v inh , input high voltage 3.5 v min dv dd = 5 v 2.5 v min dv dd = 3 v xtal1 input capacitance 18 pf typ xtal2 output capacitance 18 pf typ
rev. 0 C6C ADUC816?pecifications 1 parameter ADUC816bs unit test conditions/comments logic outputs (not including xtal2) 2 v oh , output high voltage 2.4 v min v dd = 5 v, i source = 80 a 2.4 v min v dd = 3 v, i source = 20 a v ol , output low voltage 12 0.4 v max i sink = 8 ma, sclock, sdata/mosi 0.4 v max i sink = 10 ma, p1.0 and p1.1 0.4 v i sink = 1.6 ma, all other outputs max floating state leakage current 10 a max floating state output capacitance 5 pf typ power supply monitor (psm) av dd trip point selection range 2.63 v min four trip points selectable in this range 4.63 v max programmed via tpa1? in psmcon av dd power supply trip point accuracy 3.5 % max dv dd trip point selection range 2.63 v min four trip points selectable in this range 4.63 v max programmed via tpd1? in psmcon dv dd power supply trip point accuracy 3.5 % max watchdog timer (wdt) timeout period 0 ms min nine timeout periods in this range 2000 ms max programmed via pre3? in wdcon mcu core clock rate clock rate generated via on-chip pll mcu clock rate 2 98.3 khz min programmable via cd2? bits in pllcon sfr 12.58 mhz max start-up time at power-on 300 ms typ from idle mode 1 ms typ from power-down mode oscillator running osc_pd bit = 0 in pllcon sfr wake up with int0 interrupt 1 ms typ wake up with spi/i 2 c interrupt 1 ms typ wake up with tic interrupt 1 ms typ wake up with external reset 3.4 ms typ oscillator powered down osc_pd bit = 1 in pllcon sfr wake up with external reset 0.9 sec typ after external reset in normal mode 3.3 ms typ after wdt reset in normal mode 3.3 ms typ controlled via wdcon sfr flash/ee memory reliability characteristics 13 endurance 14 100,000 cycles min data retention 15 100 years min power requirements dv dd and av dd can be set independently power supply voltage av dd , 3 v nominal operation 2.7 v min 3.6 v max av dd , 5 v nominal operation 4.75 v min 5.25 v max dv dd , 3 v nominal operation 2.7 v min 3.6 v max dv dd , 5 v nominal operation 4.75 v min 5.25 v max
rev. 0 C7C ADUC816 parameter ADUC816bs unit test conditions/comments power requirements (continued) power supply currents normal mode 16, 17 dv dd current 4 ma max dv dd = 4.75 v to 5.25 v, core clk = 1.57 mhz 2.1 ma max dv dd = 2.7 v to 3.6 v, core clk = 1.57 mhz av dd current 170 a max av dd = 5.25 v, core clk = 1.57 mhz dv dd current 15 ma max dv dd = 4.75 v to 5.25 v, core clk = 12.58 mhz 8 ma max dv dd = 2.7 v to 3.6 v, core clk = 12.58 mhz av dd current 170 a max av dd = 5.25 v, core clk = 12.58 mhz power supply currents idle mode 16, 17 dv dd current 1.2 ma max dv dd = 4.75 v to 5.25 v, core clk = 1.57 mhz 750 a typ dv dd = 2.7 v to 3.6 v, core clk = 1.57 mhz av dd current 140 a typ measured @ av dd = 5.25 v, core clk = 1.57 mhz dv dd current 2 ma typ dv dd = 4.75 v to 5.25 v, core clk = 12.58 mhz 1 ma typ dv dd = 2.7 v to 3.6 v, core clk = 12.58 mhz av dd current 140 a typ measured at av dd = 5.25 v, core clk = 12.58 mhz power supply currents power-down mode 16, 17 core clk = 1.57 mhz or 12.58 mhz dv dd current 50 a max dv dd = 4.75 v to 5.25 v, osc. on, tic on 20 a max dv dd = 2.7 v to 3.6 v, osc. on, tic on av dd current 1 a max measured at av dd = 5.25 v, osc. on or osc. off dv dd current 20 a max dv dd = 4.75 v to 5.25 v, osc. off 5 a typ dv dd = 2.7 v to 3.6 v, osc. off typical additional power supply currents core clk = 1.57 mhz, av dd = dv dd = 5 v (ai dd and di dd ) psm peripheral 50 a typ primary adc 1 ma typ auxiliary adc 500 a typ dac 150 a typ dual current sources 400 a typ notes 1 temperature range ?0 c to +85 c. 2 these numbers are not production tested but are guaranteed by design and/or characterization data on production release. 3 the primary adc is factory-calibrated at 25 c with av dd = dv dd = 5 v yielding this full-scale error. if user power supply or temperature conditions are signifi- cantly different from these, an internal full-scale calibration will restore this error to this level. 4 gain error drift is a span drift. to calculate full-scale error drift, add the offset error drift to the gain error drift times the full-scale input. 5 the auxiliary adc is factory-calibrated at 25 c with av dd = dv dd = 5 v yielding this full-scale error of ?.5 lsb. a system zero-scale and full-scale calibration will remove this error altogether. 6 dac linearity and ac specifications are calculated using: reduced code range of 48 to 4095, 0 to v ref reduced code range of 48 to 3995, 0 to v dd . 7 gain error is a measure of the span error of the dac. 8 in general terms, the bipolar input voltage range to the primary adc is given by range adc = (v ref 2 rn )/125, where: v ref = refin(+) to refin(? voltage and v ref = 1.25 v when internal adc v ref is selected. rn = decimal equivalent of rn2, rn1, rn0, e.g., v ref = 2.5 v and rn2, rn1, rn0 = 1, 1, 0 the range adc = 1.28 v. in unipolar mode the effective range is 0 v to 1.28 v in our example. 9 1.25 v is used as the reference voltage to the adc when internal v ref is selected via xref0 and xref1 bits in adc0con and adc1con respectively. 10 in bipolar mode, the auxiliary adc can only be driven to a minimum of a gnd ?30 mv as indicated by the auxiliary adc absolute ain voltage limits. the bipolar range is still ? ref to +v ref ; however, the negative voltage is limited to ?0 mv. 11 pins configured in i 2 c-compatible mode or spi mode, pins configured as digital inputs during this test. 12 pins configured in i 2 c-compatible mode only. 13 flash/ee memory reliability characteristics apply to both the flash/ee program memory and flash/ee data memory. 14 endurance is qualified to 100 kcycles as per jedec std. 22 method a117 and measured at ?0 c, +25 c and +85 c, typical endurance at 25 c is 700 kcycles. 15 retention lifetime equivalent at junction temperature (t j ) = 55 c as per jedec std. 22, method a117. retention lifetime based on an activation energy of 0.6ev will derate with junction temperature as shown in figure 27 in the flash/ee memory description section of this data sheet. 16 power supply current consumption is measured in normal, idle, and power-down modes under the following conditions: normal mode: reset = 0.4 v, digital i/o pins = open circuit, core clk changed via cd bits in pllcon, core executing internal so ftware loop. idle mode: reset = 0.4 v, digital i/o pins = open circuit, core clk changed via cd bits in pllcon, pcon.0 = 1, core execution s uspended in idle mode. power-down mode: reset = 0.4 v, all p0 pins and p1.2?1.7 pins = 0.4 v, all other digital i/o pins are open circuit, core clk c hanged via cd bits in pllcon, pcon.1 = 1, core execution suspended in power-down mode, osc turned on or off via osc_pd bit (pllcon.7) in pllcon sfr. 17 dv dd power supply current will typically increase by 3 ma (3 v operation) and 10 ma (5 v operation) during a flash/ee memory progra m or erase cycle. specifications subject to change without notice
rev. 0 ADUC816 C8C timing specifications 1, 2, 3 (av dd = 2.7 v to 3.6 v or 4.75 v to 5.25 v, dv dd = 2.7 v to 3.6 v or 4.75 v to 5.25 v; all specifications t min to t max unless otherwise noted.) 32.768 khz external crystal parameter min typ max unit figure clock input (external clock driven xtal1) t ck xtal1 period 30.52 s1 t ckl xtal1 width low 15.16 s1 t ckh xtal1 width high 15.16 s1 t ckr xtal1 rise time 20 ns 1 t ckf xtal1 fall time 20 ns 1 1/t core ADUC816 core clock frequency 4 0.098 12.58 mhz t core ADUC816 core clock period 5 0.636 s t cyc ADUC816 machine cycle time 6 0.95 7.6 122.45 s notes 1 ac inputs during testing are driven at dv dd ?0.5 v for a logic 1, and 0.45 v for a logic 0. timing measurements are made at v ih min for a logic 1, and v il max for a logic 0 as shown in figure 2. 2 for timing purposes, a port pin is no longer floating when a 100 mv change from load voltage occurs. a port pin begins to float when a 100 mv change from the loaded v oh /v ol level occurs as shown in figure 2. 3 c load for port0, ale, psen outputs = 100 pf; c load for all other outputs = 80 pf unless otherwise noted. 4 ADUC816 internal pll locks onto a multiple (384 times) the external crystal frequency of 32.768 khz to provide a stable 12.583 m hz internal clock for the system. the core can operate at this frequency or at a binary submultiple called core_clk, selected via the pllcon sfr. 5 this number is measured at the default core_clk operating frequency of 1.57 mhz. 6 ADUC816 machine cycle time is nominally defined as 12/core_clk. specifications subject to change without notice. t chk t ckl t ck t ckf t ckr figure 1. xtal1 input dv dd 0.5v 0.45v 0.2dv dd + 0.9v test points 0.2dv dd 0.1v v load 0.1v v load v load + 0.1v timing reference points v load 0.1v v load v load + 0.1v figure 2. timing waveform characteristics
rev. 0 ADUC816 C9C 12.58 mhz core_clk variable core_clk parameter min max min max unit figure external program memory t lhll ale pulsewidth 119 2t core ?40 ns 3 t avll address valid to ale low 39 t core ?40 ns 3 t llax address hold after ale low 49 t core ?30 ns 3 t lliv ale low to valid instruction in 218 4t core ?100 ns 3 t llpl ale low to psen low 49 t core ?30 ns 3 t plph psen pulsewidth 193 3t core ?45 ns 3 t pliv psen low to valid instruction in 133 3t core ?105 ns 3 t pxix input instruction hold after psen 00 ns3 t pxiz input instruction float after psen 54 t core ?25 ns 3 t aviv address to valid instruction in 292 5t core ?105 ns 3 t plaz psen low to address float 25 25 ns 3 t phax address hold after psen high 0 0 ns 3 t lhll t avll pcl (out) instruction (in) pch core_clk ale (o) psen (o) port 0 (i/o) port 2 (o) t llpl t llax t plaz t pxix t pxiz t pliv t lliv t plph t phax t aviv figure 3. external program memory read cycle
rev. 0 ADUC816 C10C 12.58 mhz core_clk variable core_clk parameter min max min max unit figure external data memory read cycle t rlrh rd pulsewidth 377 6t core ?100 ns 4 t avll address valid after ale low 39 t core ?40 ns 4 t llax address hold after ale low 44 t core ?35 ns 4 t rldv rd low to valid data in 232 5t core ?165 ns 4 t rhdx data and address hold after rd 00 ns4 t rhdz data float after rd 89 2t core ?70 ns 4 t lldv ale low to valid data in 486 8t core ?150 ns 4 t avdv address to valid data in 550 9t core ?165 ns 4 t llwl ale low to rd low 188 288 3t core ?50 3t core + 50 ns 4 t avwl address valid to rd low 188 4t core ?130 ns 4 t rlaz rd low to address float 0 0 ns 4 t whlh rd high to ale high 39 119 t core ?40 t core + 40 ns 4 t llax data (in) core_clk ale (o) psen (o) port 0 (i/o) port 2 (o) rd (o) t lldv t llwl t avwl t avll t avdv t rlaz t rldv t rhdx t rhdz t whlh a0 a7 (out) a16 a23 a8 a15 t rlrh figure 4. external data memory read cycle
rev. 0 ADUC816 C11C 12.58 mhz core_clk variable core_clk parameter min max min max unit figure external data memory write cycle t wlwh wr pulsewidth 377 6t core ?100 ns 5 t avll address valid after ale low 39 t core ?40 ns 5 t llax address hold after ale low 44 t core ?35 ns 5 t llwl ale low to wr low 188 288 3t core ?50 3t core + 50 ns 5 t avwl address valid to wr low 188 4t core ?130 ns 5 t qvwx data valid to wr transition 29 t core ?50 ns 5 t qvwh data setup before wr 406 7t core ?150 ns 5 t whqx data and address hold after wr 29 t core ?50 ns 5 t whlh wr high to ale high 39 119 t core ?40 t core + 40 ns 5 t llax a0 a7 core_clk ale (o) psen (o) port 0 (o) port 2 (o) wr (o) t whlh t whqx t wlwh t qvwx t qvwh t llwl t avwl t avll a16 a23 a8 a15 data figure 5. external data memory write cycle
rev. 0 ADUC816 C12C 12.58 mhz core_clk variable core_clk parameter min typ max min typ max unit figure uart timing (shift register mode) t xlxl serial port clock cycle time 0.95 2t core s6 t qvxh output data setup to clock 662 10t core ?133 ns 6 t dvxh input data setup to clock 292 2t core + 133 ns 6 t xhdx input data hold after clock 0 0 ns t xhqx output data hold after clock 42 2t core ?117 ns 6 set ri or set ti 01 bit 1 t xlxl ale (o) txd (output clock) rxd (output data) rxd (input data) 67 bit 6 msb msb bit 6 bit 1 lsb t xhqx t qvxh t dvxh t xhdx figure 6. uart timing in shift register mode
rev. 0 ADUC816 C13C parameter min max unit figure i 2 c-compatible interface timing t l sclock low pulsewidth 4.7 s7 t h sclock high pulsewidth 4.0 s7 t shd start condition hold time 0.6 s7 t dsu data setup time 100 s7 t dhd data hold time 0.9 s7 t rsu setup time for repeated start 0.6 s7 t psu stop condition setup time 0.6 s7 t buf bus free time between a stop 1.3 s7 condition and a start condition t r rise time of both sclock and sdata 300 ns 7 t f fall time of both sclock and sdata 300 ns 7 t sup * pulsewidth of spike suppressed 50 ns 7 * input filtering on both the sclock and sdata inputs suppresses noise spikes less than 50 ns. sdata (i/o) stop condition ack msb sclk (i) t psu t shd t dsu t dhd t sup t h t dsu t dhd t rsu t f t r t f t r t l t buf start condition t sup lsb msb 1 2-7 8 ps 9 s(r) repeated start 1 figure 7. i 2 c-compatible interface timing
rev. 0 ADUC816 C14C parameter min typ max unit figure spi master mode timing (cpha = 1) t sl sclock low pulsewidth * 630 ns 8 t sh sclock high pulsewidth * 630 ns 8 t dav data output valid after sclock edge 50 ns 8 t dsu data input setup time before sclock edge 100 ns 8 t dhd data input hold time after sclock edge 100 ns 8 t df data output fall time 10 25 ns 8 t dr data output rise time 10 25 ns 8 t sr sclock rise time 10 25 ns 8 t sf sclock fall time 10 25 ns 8 * characterized under the following conditions: a. core clock divider bits cd2, cd1, and cd0 bits in pllcon sfr set to 0, 1, and 1 respectively, i.e., core clock frequency = 1. 57 mhz and b. spi bit-rate selection bits spr1 and spr0 bits in spicon sfr set to 0 and 0 respectively. sclock (cpol = 0) t sh sclock (cpol = 1) mosi miso bits 6 1 lsb msb t sl t dav t df t dr t sr t sf t dhd t dsu msb in bits 6 1 lsb in figure 8. spi master mode timing (cpha = 1)
rev. 0 ADUC816 C15C parameter min typ max unit figure spi master mode timing (cpha = 0) t sl sclock low pulsewidth * 630 ns 9 t sh sclock high pulsewidth * 630 ns 9 t dav data output valid after sclock edge 50 ns 9 t dosu data output setup before sclock edge 150 ns 9 t dsu data input setup time before sclock edge 100 ns 9 t dhd data input hold time after sclock edge 100 ns 9 t df data output fall time 10 25 ns 9 t dr data output rise time 10 25 ns 9 t sr sclock rise time 10 25 ns 9 t sf sclock fall time 10 25 ns 9 * characterized under the following conditions: a. core clock divider bits cd2, cd1 and cd0 bits in pllcon sfr set to 0, 1, and 1 respectively, i.e., core clock frequency = 1.5 7 mhz and b. spi bit-rate selection bits spr1 and spr0 bits in spicon sfr set to 0 and 0 respectively. sclock (cpol = 0) t dsu sclock (cpol = 1) mosi miso msb lsb lsb in bits 6 1 bits 6 1 msb in t dhd t dr t dav t df t dosu t sh t sl t sr t sf figure 9. spi master mode timing (cpha = 0)
rev. 0 ADUC816 C16C parameter min typ max unit figure spi slave mode timing (cpha = 1) t ss ss to sclock edge 0 ns 10 t sl sclock low pulsewidth 330 ns 10 t sh sclock high pulsewidth 330 ns 10 t dav data output valid after sclock edge 50 ns 10 t dsu data input setup time before sclock edge 100 ns 10 t dhd data input hold time after sclock edge 100 ns 10 t df data output fall time 10 25 ns 10 t dr data output rise time 10 25 ns 10 t sr sclock rise time 10 25 ns 10 t sf sclock fall time 10 25 ns 10 t sfs ss high after sclock edge 0 ns 10 sclock (cpol = 0) t ss sclock (cpol = 1) miso mosi ss msb in bits 6 1 lsb in lsb bits 6 1 msb t dhd t dsu t df t dr t sl t sh t dav t df t sr t sf t sfs figure 10. spi slave mode timing (cpha = 1)
rev. 0 ADUC816 C17C parameter min typ max unit figure spi slave mode timing (cpha = 0) t ss ss to sclock edge 0 ns 11 t sl sclock low pulsewidth 330 ns 11 t sh sclock high pulsewidth 330 ns 11 t dav data output valid after sclock edge 50 ns 11 t dsu data input setup time before sclock edge 100 ns 11 t dhd data input hold time after sclock edge 100 ns 11 t df data output fall time 10 25 ns 11 t dr data output rise time 10 25 ns 11 t sr sclock rise time 10 25 ns 11 t sf sclock fall time 10 25 ns 11 t ssr ss to sclock edge 50 ns 11 t doss data output valid after ss edge 20 ns 11 t sfs ss high after sclock edge 0 ns 11 miso mosi sclock (cpol = 1) sclock (cpol = 0) ss msb bits 6 1 lsb bits 6 1 msb in t dhd t dsu t dr t df t dav t doss t sh t sl t ss t sr t sf t sfs lsb in figure 11. spi slave mode timing (cpha = 0)
rev. 0 ADUC816 C18C caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ADUC816 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. warning! esd sensitive device absolute maximum ratings 1 (t a = 25 c unless otherwise noted) av dd to agnd . . . . . . . . . . . . . . . . . . . . . . . ?.3 v to +7 v av dd to dgnd . . . . . . . . . . . . . . . . . . . . . . . ?.3 v to +7 v dv dd to agnd . . . . . . . . . . . . . . . . . . . . . . . ?.3 v to +7 v dv dd to dgnd . . . . . . . . . . . . . . . . . . . . . . . ?.3 v to +7 v agnd to dgnd 2 . . . . . . . . . . . . . . . . . . . ?.3 v to +0.3 v av dd to dv dd . . . . . . . . . . . . . . . . . . . . . . . . . 2 v to +5 v analog input voltage to agnd 3 . . . . ?.3 v to av dd +0.3 v reference input voltage to agnd . . ?.3 v to av dd +0.3 v ain/refin current (indefinite) . . . . . . . . . . . . . . . . 30 ma digital input voltage to dgnd . . . . ?.3 v to dv dd +0.3 v digital output voltage to dgnd . . . ?.3 v to dv dd +0.3 v operating temperature range . . . . . . . . . . . ?0 c to +85 c storage temperature range . . . . . . . . . . . . ?5 c to +150 c junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . 150 c ja thermal impedance . . . . . . . . . . . . . . . . . . . . . . . 90 c/w lead temperature, soldering vapor phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . 215 c infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 c notes 1 stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 agnd and dgnd are shorted internally on the ADUC816. 3 applies to p1.2 to p1.7 pins operating in analog or digital input modes. pin configuration 52-lead mqfp ADUC816 top view (not to scale) pin 1 in dentifier 1 13 14 26 40 52 27 39 ordering guide model temperature range package description package option ADUC816bs ?0 c to +85 c 52-lead plastic quad flatpack s-52 quickstart development system model description eval-ADUC816qs development system for the ADUC816 microconverter, containing: evaluation board serial port cable plug-in power supply windows serial downloader (wsd) windows debugger (debug) windows ADUC816 simulator (adsim) windows adc analysis software program (wasp) 8051 assembler (metalink) c-compiler (keil) evaluation copy limited to 2 kcode example code documentation windows is a registered trademark of microsoft corporation.
rev. 0 ADUC816 C19C pin function descriptions pin no. mnemonic type * description 1 p1.0/t2 i/o port 1.0 can function as a digital input or digital output and has a pull-up configu- ration as described below for port 3. p1.0 has an increased current drive sink capa bility of 10 ma and can also be used to provide a clock input to timer 2. when enabled, counter 2 is incremented in response to a negative transition on the t2 input pin. 2 p1.1/t2ex i/o port 1.1 can function as a digital input or digital output and has a pull-up configu- ration as described below for port 3. p1.1 has an increased current drive sink capability of 10 ma and can also be used to provide a control input to timer 2. when enabled, a negative transition on the t2ex input pin will cause a timer 2 capture or reload event. 3 p1.2/dac/iexc1 i/o port 1.2. this pin has no digital output driver; it can function as a digital input for which 0 must be written to the port bit. as a digital input, p1.2 must be driven high or low externally. the voltage output from the dac can also be configured to appear at this pin. if the dac output is not being used, one or both of the excita- tion current sources (200 a or 2 200 a) can be programmed to be sourced at this pin. 4 p1.3/ain5/iexc2 i port 1.3. this pin has no digital output driver, it can function as a digital input for which 0 must be written to the port bit. as a digital input, p1.3 must be driven high or low externally. this pin can provide an analog input (ain5) to the auxiliary adc and one or both of the excitation current sources (200 a or 2 200 a) can be programmed to be sourced at this pin. 5av dd s analog supply voltage, 3 v or 5 v. 6 agnd s analog ground. ground reference pin for the analog circuitry. 7 refin(? i reference input, negative terminal. 8 refin(+) i reference input, positive terminal. 9?1 p1.4?1.6 i port 1.4 to p1.6. these pins have no digital output drivers; they can function as digital inputs, for which 0 must be written to the respective port bit. as a digital input, these pins must be driven high or low externally. these port pins also have the following analog functionality: p1.4/ain1 i primary adc channel, positive analog input p1.5/ain2 i primary adc channel, negative analog input p1.6/ain3 i auxiliary adc input or muxed primary adc channel, positive analog input 12 p1.7/ain4/dac i/o port 1.7. this pin has no digital output driver; it can function as a digital input for which 0 must be w ritten to the port bit. as a digital input, p1.7 must be driven high or low externally. this pin can provide an analog input (ain4) to the auxiliary adc or muxed primary adc channel, negative analog input. the voltage output from the dac can also be configured to appear at this pin. 13 ss i slave select input for the spi interface. a weak pull-up is present on this pin. 14 miso i/o master input/slave output for the spi interface. there is a weak pull-up on this input pin. 15 reset i reset input. a high level on this pin for 24 core clock cycles while the oscillator is running resets the device. there is a weak pull-down and a schmitt trigger input stage on this pin. 16?9 p3.0?3.3 i/o p3.0?3.3 are bidirectional port pins with internal pull-up resistors. port 3 pins that have 1s written to them are pulled high by the internal pull-up resistors, and in that state can be used as inputs. as inputs, port 3 pins being pulled externally low will source current because of the internal pull-up resistors. when driving a 0-to-1 output transition, a strong pull-up is active for two core clock periods of the instruction cycle. port 3 pins also have various secondary functions described below. p3.0/rxd i/o receiver data input (asynchronous) or data input/output (synchronous) of serial (uart) port. p3.1/txd i/o transmitter data output (asynchronous) or clock output (synchronous) of serial (uart) port. p3.2/ int0 i/o interrupt 0, programmable edge or level triggered interrupt input, which can be programmed to one of two priority levels. this pin can also be used as a gate con- trol input to timer 0.
rev. 0 ADUC816 C20C pin no. mnemonic type * description 16?9 p3.0?3.3 ( continued) p3.3/ int1 i/o interrupt 1, programmable edge-or level-triggered interrupt input, which can be programmed to one of two priority levels. this pin can also be used as a gate con- trol input to timer1. 20, 34, 48 dv dd s digital supply, 3 v or 5 v. 21, 35, 47 dgnd s digital ground, ground reference point for the digital circuitry. 22?5 p3.4?3.7 i/o p3.4?3.7 are bidirectional port pins with internal pull-up resistors. port 3 pins that have 1s written to them are pulled high by the internal pull-up resistors, and in that state can be used as inputs. as inputs, port 3 pins being pulled externally low will source current because of the internal pull-up resistors. when driving a 0-to-1 out- put transition, a strong pull-up is active for two core clock periods of the instruction cycle. port 3 pins also have various secondary functions described below. p3.4/t0 i/o timer/counter 0 input. p3.5/t1 i/o timer/counter 1 input. p3.6/ wr i/o write control signal, logic output. latches the data byte from port 0 into an external data memory. p3.7/ rd i/o read control signal, logic output. enables the data from an external data memory to port 0. 26 sclk i/o serial interface clock for either the i 2 c-compatible or spi interface. as an input this pin is a schmitt-triggered input and a weak internal pull-up is present on this pin unless it is outputting logic low. 27 sdata/mosi i/o serial data i/o for the i 2 c-compatible interface or master output/slave input for the spi interface. a weak internal pull-up is present on this pin unless it is outputting logic low. 28?1 p2.0?2.3 i/o port 2 is a bidirectional port with internal pull-up resistors. port 2 pins that have 1s (a8?11) written to them are pulled high by the internal pull-up resistors, and in that state can (a16?19) be used as inputs. as inputs, port 2 pins being pulled externally low will source current because of the internal pull-up resistors. port 2 emits the high order address bytes during fetches from external program memory and middle and high order address bytes during accesses to the 24-bit external data memory space. 32 xtal1 i input to the crystal oscillator inverter. 33 xtal2 o output from the crystal oscillator inverter. 36?9 p2.4?2.7 i/o port 2 is a bidirectional port with internal pull-up resistors. port 2 pins that have 1s (a12?15) written to them are pulled high by the internal pull-up resistors, and in that state they (a20?23) can be used as inputs. as inputs, port 2 pins being pulled externally low will source current because of the internal pull-up resistors. port 2 emits the high order address bytes during fetches from external program memory and middle and high order address bytes during accesses to the 24-bit external data memory space. 40 ea i/o external access enable, logic input. when held high, this input enables the device to fetch code from internal program memory locations 0000h to 1fffh. when held low, this input enables the device to fetch all instructions from external program memory. to determine the mode of code execution, i.e., internal or external, the ea pin is sampled at the end of an external reset assertion or as part of a device power cycle. ea may also be used as an external emulation i/o pin and therefore the voltage level at this pin must not be changed during normal mode operation as it may cause an emulation interrupt that will halt code execution. 41 psen o program store enable, logic output. this output is a control signal that enables the external program memory to the bus during external fetch operations. it is active every six oscillator periods except during external data memory accesses. this pin remains high during internal program execution. psen can also be used to enable serial download mode when pulled low through a resistor at the end of an external reset assertion or as part of a device power cycle. 42 ale o address latch enable, logic output. this output is used to latch the low byte (and page byte for 24-bit data address space accesses) of the address to external memory during external code or data memory access cycles. it is activated every six oscillator periods except during an external data memory access. it can be disabled by setting the pcon.4 bit in the pcon sfr.
rev. 0 ADUC816 C21C pin no. mnemonic type * description 43?6 p0.0?0.3 i/o p0.0?0.3, these pins are part of port0 which is an 8-bit open-drain bidirectional (ad0?d3) i/o port. port 0 pins that have 1s written to them float and in that state can be used as high impedance inputs. an external pull-up resistor will be required on p0 out- put outputs to force a valid logic high level externally. port 0 is also the multiplexed low-order address and data bus during accesses to external program or data memory. in this application it uses strong internal pull-ups when emitting 1s. 49?2 p0.4?0.7 i/o p0.4?0.7, these pins are part of port0 which is an 8-bit open drain bidirectional (ad4?d7) i/o port. port 0 pins that have 1s written to them float and in that state can be used as high impedance inputs. port 0 is also the multiplexed low-order address and data bus during accesses to external program or data memory. in this application it uses strong internal pull-ups when emitting 1s. * i = input, o = output, s = supply. notes 1. in the following descriptions, set implies a logic 1 state and cleared implies a logic 0 state unless otherwise stated. 2. in the following descriptions, set and cleared also imply that the bit is automatically set or cleared by the ADUC816 hardwar e unless otherwise stated. 3. user software should not write 1s to reserved or unimplemented bits as they may be used in future products. \ prog. clock divider watchdog timer 256 8 user ram power supply monitor ain3 ain4 ain5 ain1 ain2 refin refin iexc 2 iexc 1 ain mux temp sensor ain mux bandgap reference v ref detect current source mux 200 a 200 a 5 av dd 6 agnd 20 dv dd 34 dv dd 48 dv dd 21 dgnd 35 dgnd 47 dgnd 15 reset 26 sclk 27 sdata/mosi 14 miso 13 ss xtal1 buf ADUC816 auxiliary adc 16-bit adc adc control and calibration pga primary adc 16-bit adc adc control and calibration 3 22 t0 23 t1 2 t2ex t2 1 18 int0 19 int1 dac 40 ea 41 psen 17 txd 16 rxd 640 8 data flash/ee 8k 8 program flash/ee asynchronous serial port (uart) 8052 mcu core downloader debugger 42 ale dac control buf single-pin emulator synchronous serial interface (spi or i 2 c) 16-bit counter timers time interval counter xtal2 osc and pll 43 p0.0 (ad0) 44 p0.1 (ad1) 45 p0.2 (ad2) 46 p0.3 (ad3) 49 p0.4 (ad4) 50 p0.5 (ad5) 51 p0.6 (ad6) 52 p0.7 (ad7) 1 p1.0 (t2) 2 p1.1 (t2ex) 3 p1.2 (dac/iexc 1) 4 9 p1.4 (ain1) 10 p1.5 (ain2) 11 p1.6 (ain3) 12 p1.7 (ain4/dac) 28 p2.0 ( a8/a16) 29 p2.1 (a9/a17) 30 p2.2 ( a10/a18) 31 p2.3 (a11/a19) 36 p2.4 ( a12/a20) 37 p2.5 ( a13/a21) 38 p2.6 ( a14/a22) 39 p2.7 ( a15/a23) 16 p3.0 (rxd) 17 p3.1 (txd) 18 p3.2 ( int0 ) 19 p3.3 ( int1 ) 22 p3.4 (t0) 23 p3.5 (t1) 24 p3.6 ( wr ) 25 p3.7 ( rd ) 12-bit voltage output dac p1.3 (ain5/iexc 2) 32 33 figure 12. block diagram
rev. 0 ADUC816 C22C memory organization as with all 8051-compatible devices, the ADUC816 has sepa- rate address spaces for program and data memory as shown in figure 13 and figure 14. if the user applies power or resets the device while the ea pin is pulled low, the part will execute code from the external pro- gram space, otherwise the part defaults to code execution from its internal 8 kbyte flash/ee program memory. this internal code space can be downloaded via the uart serial port while the device is in-circuit. external program memory space ffffh 2000h 1fffh 0000h ea = 1 internal 8 kbyte flash/ee program memory program memory space read only ea = 0 external program memory space figure 13. program memory map the data memory address space consists of internal and exter- nal memory space. the internal memory space is divided into four physically separate and distinct blocks, namely the lower 128 bytes of ram, the upper 128 bytes of ram, the 128 bytes of special function register (sfr) area, and a 640-byte flash/ee data memory. while the upper 128 bytes of ram, and the sfr area share the same address locations, they are accessed through different address modes. the lower 128 bytes of data memory can be accessed through direct or indirect addressing, the upper 128 bytes of ram can be accessed through indirect addressing, and the sfr area is accessed through direct addressing. also, as shown in figure 13, the additional 640 bytes of flash/ee data memory are available to the user and can be accessed indirectly via a group of control registers mapped into the special function register (sfr) area. access to the flash/ ee data memory is discussed in detail later as part of the f lash/ ee memory section in this data sheet. the external data memory area can be expanded up to 16 mbytes. this is an enhancement of the 64 kbyte external data memory space available on standard 8051-compatible cores. the external data memory is discussed in more detail in the ADUC816 hardware design considerations section. special function registers accessible by direct addressing only 640 bytes flash/ee data memory accessed indirectly via sfr control registers internal data memory space ffh 80h 7fh 00h upper 128 ffh 80h external data memory space (24-bit address space) 000000h data memory space read/write (page 159) (page 0) 00h 9fh ffffffh lower 128 accessible by indirect addressing only accessible by direct and indirect addressing figure 14. data memory map the lower 128 bytes of internal data memory are mapped as shown in figure 15. the lowest 32 bytes are grouped into four banks of eight registers addressed as r0 through r7. the next 16 bytes (128 bits), locations 20hex through 2fhex above the register banks, form a block of directly addressable bit locations at bit addresses 00h through 7fh. the stack can be located anywhere in the internal memory address space, and the stack depth can be expanded up to 256 bytes. bit-addressable (bit addresses) four banks of eight registers r0 r7 banks selected via bits in psw 11 10 01 00 07h 0fh 17h 1fh 2fh 7fh 00h 08h 10h 18h 20h reset value of stack pointer 30h general-purpose area figure 15. lower 128 bytes of internal data memory
rev. 0 ADUC816 C23C reset initializes the stack pointer to location 07 hex and increm ents it once to start from locations 08 hex which is also the first regis- ter (r0) of register bank 1. thus, if one is going to use more than one register bank, the stack pointer should be initialized to an area of ram not used for data storage. the sfr space is mapped to the upper 128 bytes of internal data memory space and accessed by direct addressing only. it provides an interface between the cpu and all on-chip peripherals. a block diagram showing the programming model of the ADUC816 via the sfr area is shown in figure 16. a complete sfr map is shown in figure 17. 128-byte special function register area 8 kbyte electrically reprogrammable nonvolatile flash/ee program memory 8051- compatible core other on-chip peripherals temperature sensor current sources 12-bit dac serial i/o wdt psm tic pll dual sigma-delta adcs 640-byte electrically reprogrammable nonvolatile flash/ee data memory 256 bytes ram figure 16. programming model overview of mcu-related sfrs accumulator sfr acc is the accumulator register and is used for math operations including addition, subtraction, integer multiplication and division, and boolean bit manipulations. the mnemonics for accumulator- specific instructions refer to the accumulator as a. b sfr the b register is used with the acc for multiplication and divi- sion operations. for other instructions it can be treated as a general-purpose scratchpad register. stack pointer sfr the sp register is the stack pointer and is used to hold an internal ram address that is called the top of the stack. the sp register is incr emented before data is stored during push and call executions. while the stack may reside anywhere in on-chip ram, the sp register is initialized to 07h after a reset. this causes the stack to begin at location 08h. data pointer the data pointer is made up of three 8-bit registers, named dpp (page byte), dph (high byte) and dpl (low byte). these are used to provide memory addresses for internal and external code access and external data access. it may be m anipulated as a 16-bit register (dptr = dph, dpl), although inc dptr instructions will automatically carry over to dpp, or as three independent 8-bit registers (dpp, dph, dpl). program status word sfr the psw register is the program status word which contains several bits reflecting the current status of the cpu as detailed in table i. sfr address d0h power on default value 00h bit addressable yes y cc a0 f1 s r0 s rv o1 fp table i. psw sfr bit designations bit name description 7 cy carry flag 6 ac auxiliary carry flag 5 f0 general-purpose flag 4 rs1 register bank select bits 3 rs0 rs1 rs0 selected bank 000 011 102 113 2 ov overflow flag 1 f1 general-purpose flag 0 p parity bit power control sfr the power control (pcon) register contains bits for power- saving options and general-purpose status flags as shown in table ii. sfr address 87h power on default value 00h bit addressable no d o m sd p i r e sd p 0 t n if f o e l a1 f g0 f gd pl d i table ii. pcon sfr bit designations bit name description 7 smod double uart baud rate 6 seripd i 2 c/spi power-down interrupt enable 5 int0pd int0 power-down interrupt enable 4 aleoff disable ale output 3 gf1 general-purpose flag bit 2 gf0 general-purpose flag bit 1 pd power-down mode enable 0 idl idle mode enable
rev. 0 ADUC816 C24C special function registers all registers except the program counter and the four general- purpose register banks, reside in the sfr area. the sfr re gisters include control, configuration, and data registers that provide an interface between the cpu and all on-chip peripherals. figure 17 shows a full sfr memory map and sfr contents on reset; not used indicates unoccupied sfr locations. u noc- cupied locations in the sfr address space are not implemented; i.e., no register exists at this location. if an unoccupied location is read, an unspecified value is returned. sfr locations reserved for future use are shaded (reserved) and should not be accessed by user software. spicon f8h 04h reserved reserved reserved reserved reserved reserved not used reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved not used not used not used not used not used not used not used not used not used not used not used not used reserved reserved reserved reserved reserved not used dacl fbh 00h dach fch 00h daccon fdh 00h b f0h 00h i2ccon e8h 00h acc e0h 00h adcstat d8h 00h psw d0h 00h t2con 00h wdcon c0h 10h ip b8h 00h p3 b0h ffh ie a8h 00h p2 a0h ffh scon 98h 00h p1 90h ffh tcon 88h 00h p0 80h ffh adcmode d1h 00h econ b9h 00h ieip2 a9h a0h timecon a1h 00h sbuf 99h 00h tmod 89h 00h sp 81h 07h not used eah 55h of0m * e2h 00h adc0m dah 00h adc0con d2h 07h rcap2l cah 00h chipid c2h 16h hthsec a2h 00h i2cdat 9ah 00h tl0 8ah 00h dpl 82h 00h ebh 53h of0h * e3h 80h adc0h dbh 00h adc1con d3h 00h rcap2h cbh 00h sec a3h 00h tl1 8bh 00h dph 83h 00h reserved reserved reserved reserved reserved i2cdat 00h 9bh gn1l * ech 9ah of1l * e4h 00h adc1l dch 00h sf d4h 45h tl2 cch 00h edata1 bch 00h min a4h 00h th0 8ch 00h dpp 84h 00h reserved gn1h * edh 59h of1h * e5h 80h adc1h ddh 00h icon d5h 00h th2 cdh 00h edata2 bdh 00h hour a5h 00h th1 8dh 00h reserved eadrl c6h 00h edata3 beh 00h intval a6h 00h spidat f7h 00h psmcon dfh deh pllcon d7h 03h edata4 bfh 00h pcon 87h 00h gn0m * gn0h * c8h not used not used not used reserved reserved reserved ispi ffh 0 wcol feh 0 spe fdh 0 spim fch 0 cpol fbh 0 cpha fah spr1 f9h 0 spr0 f8h 0 bits f7h 0 f6h 0 f5h 0 f4h 0 f3h 0 f2h f1h 0 f0h 0 bits mdo efh 0 mde eeh 0 mco edh 0 mdi ech 0 i2cm ebh 0 i2crs eah i2ctx e9h 0 i2ci e8h 0 bits e7h 0 e6h 0 e5h 0 e4h 0 e3h 0 e2h e1h 0 e0h 0 bits rdy0 dfh 0 rdy1 deh 0 cal ddh 0 noxref dch 0 err0 dbh 0 err1 dah d9h 0 d8h 0 bits cy d7h 0 ac d6h 0 f0 d5h 0 rsi d4h 0 rs0 d3h 0 ov d2h fi d1h 0 p d0h 0 bits tf2 cfh 0 exf2 ceh 0 rclk cdh 0 tclk cch 0 exen2 cbh 0 tr2 cah cnt2 c9h 0 cap2 c8h 0 bits pre2 c7h 0 pre1 c6h 0 pre0 c5h 0 c4h 1 wdir c3h 0 wds c2h wde c1h 0 wdwr c0h 0 bits bfh 0 padc beh 0 pt2 bdh 0 ps bch 0 pt1 bbh 0 px1 bah pt0 b9h 0 px0 b8h 0 bits rd b7h 1 wr b6h 1 t1 b5h 1 t0 b4h 1 int1 b3h 1 int0 b2h txd b1h 1 rxd b0h 1 bits ea afh eadc aeh et2 adh es ach 0 et1 abh 0 ex1 aah et0 a9h 0 ex0 a8h 0 bits a7h a6h a5h 1 a4h 1 a3h 1 a2h a1h 1 a0h 1 bits sm0 9fh 0 sm1 9eh 0 sm2 9dh 0 ren 9ch 0 tb8 9bh 0 rb8 9ah t1 99h 0 r1 98h 0 bits 97h 1 96h 1 95h 1 94h 1 93h 1 92h t2ex 91h 1 t2 90h 1 bits tf1 8fh 0 tr1 8eh 0 tf0 8dh 0 tr0 8ch 0 ie1 8bh 0 it1 8ah ie0 89h 0 it0 88h 0 bits 87h 1 86h 1 85h 1 84h 1 83h 1 82h 81h 1 80h 1 bits 1 1 0 1 0 1 1 0 0 0 0 0 0 0 pre3 000 0 11 * calibration coefficients are preconfigured at power-up to factory-calibrated values. ie0 89h 0 it0 88h 0 tcon 88h 00h bit mnemonic bit bit address mnemonic default value sfr address these bits are contained in this byte. default bit value sfr map key: sfr note: sfrs whose addresses end in 0h or 8h are bit-addressable. figure 17. special function register locations and reset values
rev. 0 ADUC816 C25C sfr interface to the primary and auxiliary adcs both adcs are controlled and configured via a number of sfrs that are mentioned here and described in more detail in the following pages. adcstat: adc status register. holds general status of the primary and auxiliary adcs. adcmode: adc mode register. controls general modes of operation for primary and auxiliary adcs. adc0con: primary adc control register. controls specific configuration of primary adc. adc1con: auxiliary adc control register. controls specific configuration of auxiliary adc. sf: sinc filter register. configures the decima tion factor for the sinc3 filter and thus the primary and auxiliary adc update rates. icon: c urrent source control register. allows user control of the various on-chip current source options. adc0h/m * : primary adc 16-bit conversion result held in these two 8-bit registers. adc1h/l: auxiliary adc 16-bit conversion result held in these two 8-bit registers. of0h/m * : primary adc 16-bit offset calibration coeffi- cient held in these two 8-bit registers. of1h/l: auxiliary adc 16-bit offset calibration coeffi- cient held in these two 8-bit registers. gn0h/m * : primary adc 16-bit gain calibration coeffi- cient held in these two 8-bit registers. gn1h/l: auxiliary adc 16-bit gain calibration coeffi- cient held in these two 8-bit registers. * to maintain code compatibility with the aduc824, it is the low-byte sfr associated with these register groups that is omitted on the ADUC816. adcstat (adc status register) this sfr reflects the status of both adcs including data ready, calibration and various (adc-related) error and warning condi- tions including reference detect and conversion overflow/underflow flags. sfr address d8h power-on default value 00h bit addressable yes 0 y d r1 y d rl a cf e r x o n0 r r e1 r r e- - -- - - table iii. adcstat sfr bit designations bit name description 7 rdy0 ready bit for primary adc. set by hardware on completion of adc conversion or calibration cycle. cleared directly by the user or indirectly by write to the mode bits to start another primary adc conversion or calibration. the primary adc is inhibited from writing further results to its data or calibration registers until the rdy0 bit is cleared. 6 rdy1 ready bit for auxiliary adc. same definition as rdy0 referred to the auxiliary adc. 5 cal calibration status bit. set by hardware on completion of calibration. cleared indirectly by a write to the mode bits to start another adc conversion or calibration. 4 noxref no external reference bit (only active if primary or auxiliary adc is active). set to indicate that one or both of the refin pins is floating or the applied voltage is below a specified threshold. when set conversion results are clamped to all ones,if using ext. reference. cleared to indicate valid v ref . 3 err0 primary adc error bit. set by hardware to indicate that the result written to the primary adc data registers has been clamped to all zeros or all ones. after a calibration this bit also flags error conditions that caused the calibra tion registers not to be written. cleared by a write to the mode bits to initiate a conversion or calibration. 2 err1 auxiliary adc error bit. same definition as err0 referred to the a uxiliary adc. 1 --- reserved for future use. 0 --- reserved for future use.
rev. 0 ADUC816 C26C adcmode (adc mode register) used to control the operational mode of both adcs. sfr address d1h power-on default value 00h bit addressable no - - -- - -n e 0 c d an e 1 c d a- - -2 d m1 d m0 d m table iv. adcmode sfr bit designations bit name description 7 --- reserved for future use. 6 --- reserved for future use. 5 adc0en primary adc enable. set by the user to enable the primary adc and place it in the mode selected in md2-md0 below cleared by the user to place the primary adc in power-down mode. 4 adc1en auxiliary adc enable. set by the user to enable the auxiliary adc and place it in the mode selected in md2-md0 below cleared by the user to place the auxiliary adc in power-down mode. 3 --- reserved for future use. 2 md2 primary and auxiliary adc mode bits. 1 md1 these bits select the operational mode of the enabled adc as follows: 0 md0 md2 md1 md0 0 0 0 power-down mode (power-on default) 0 0 1 idle mode in idle mode the adc filter and modulator are held in a reset state although the modulator clocks are still provided. 0 1 0 single conversion mode in single conversion mode, a single conversion is performed on the enabled adc. on completion of the conversion, the adc data regis- ters (adc0h/m and/or adc1h/l) are updated, the relevant flags in the adcstat sfr are written, and power-down is re-entered with the md2?d0 accordingly being written to 000. 0 1 1 continuous conversion in continuous conversion mode the adc data registers are regularly updated at the selected update rate (see sf register) 1 0 0 internal zero-scale calibration internal short automatically connected to the enabled adc(s) 1 0 1 internal full-scale calibration internal or external v ref (as determined by xref0 and xref1 bits in adc0/1con) is automatically connected to the adc input for this calibration. 1 1 0 system zero-scale calibration user should connect system zero-scale input to the adc input pins as selected by ch1/ch0 and ach1/ach0 bits in the adc0/1con register. 1 1 1 system full-scale calibration user should connect system full-scale input to the adc input pins as selected by ch1/ch0 and ach1/ach0 bits in the adc0/1con register. notes 1. any change to the md bits will immediately reset both adcs. a write to the md2? bits with no change is also treated as a res et. (see exception to this in note 3 below.) 2. if adc0con is written when ad0en = 1, or if ad0en is changed from 0 to 1, then both adcs are also immediately reset. in other words, the primary adc is given priority over the auxiliary adc and any change requested on the primary adc is immediately responded to. 3. on the other hand, if adc1con is written or if adc1en is changed from 0 to 1, only the auxiliary adc is reset. for example, i f the primary adc is continuously converting when the auxiliary adc change or enable occurs, the primary adc continues undisturbed. rather than allow the auxilia ry adc to operate with a phase difference from the primary adc, the auxiliary adc will fall into step with the outputs of the primary adc. the result is that the first conversion time for the auxiliary adc will be delayed up to three outputs while the auxiliary adc update rate is synchronized to the primary adc. 4. once adcmode has been written with a calibration mode, the rdy0/1 bits (adcstat) are immediately reset and the calibration co mmences. on completion, the appropriate calibration registers are written, the relevant bits in adcstat are written, and the md2? bits are reset to 00 0 to indicate the adc is back in power-down mode. 5. any calibration request of the auxiliary adc while the temperature sensor is selected will fail to complete. although the rdy 1 bit will be set at the end of the calibration cycle, no update of the calibration sfrs will take place and the err1 bit will be set. 6. calibrations are performed at maximum sf (see sf sfr) value guaranteeing optimum calibration operation.
rev. 0 ADUC816 C27C adc0con (primary adc control register) used to configure the primary adc for range, channel selection, external ref enable, and unipolar or bipolar coding. sfr address d2h power-on default value 07h bit addressable no - - -0 f e r x1 h c0 h c0 i n u2 n r1 n r0 n r table v. adc0con sfr bit designations bit name description 7 --- reserved for future use. 6 xref0 primary adc external reference select bit. set by user to enable the primary adc to use the external reference via refin(+)/refin(?. cleared by user to enable the primary adc to use the internal bandgap reference (v ref = 1.25 v). 5 ch1 primary adc channel selection bits. 4 ch0 written by the user to select the differential input pairs used by the primary adc as follows: ch1 ch0 positive input negative input 0 0 ain1 ain2 0 1 ain3 ain4 1 0 ain2 ain2 (internal short) 1 1 ain3 ain2 3 uni0 primary adc unipolar bit. set by user to enable unipolar coding, i.e., zero differential input will result in 000000 hex output. cleared by user to enable bipolar coding, zero differential input will result in 800000 hex output. 2 rn2 primary adc range bits. 1 rn1 written by the user to select the primary adc input range as follows: 0 rn0 rn2 rn1 rn0 selected primary adc input range (v ref = 2.5 v) 000 20 mv 001 40 mv 010 80 mv 011 160 mv 100 320 mv 101 640 mv 110 1.28 v 111 2.56 v
rev. 0 ADUC816 C28C adc1con (auxiliary adc control register) used to configure the auxiliary adc for channel selection, external ref enable and unipolar or bipolar coding. it should be not ed that the auxiliary adc only operates on a fixed input range of v ref . sfr address d3h power-on default value 00h bit addressable no - - -1 f e r x1 h c a0 h c a1 i n u- - -- - -- - - table vi. adc1con sfr bit designations bit name description 7 --- reserved for future use. 6 xref1 auxiliary adc external reference bit. set by user to enable the auxiliary adc to use the external reference via refin(+)/refin(?. cleared by user to enable the auxiliary adc to use the internal bandgap reference. 5 ach1 auxiliary adc channel selection bits. 4 ach0 written by the user to select the single-ended input pins used to drive the auxiliary adc as follows: ach1 ach0 positive input negative input 0 0 ain3 agnd 0 1 ain4 agnd 1 0 temp sensor * agnd (temp. sensor routed to the adc input) 1 1 ain5 agnd 3 uni1 auxiliary adc unipolar bit. set by user to enable unipolar coding, i.e., zero input will result in 0000 hex output. cleared by user to enable bipolar coding, zero input will result in 8000 hex output. 2 --- reserved for future use. 1 --- reserved for future use. 0 --- reserved for future use. * notes 1. when the temperature sensor is selected, user code must select internal reference via xref1 bit above and clear the uni1 bit (adc1con.3) to select bipolar coding. 2. the temperature sensor is factory calibrated to yield conversion results 8000h at 0 c. 3. a +1 c change in temperature will result in a +1 lsb change in the adc1h register adc conversion result. sf (sinc filter register) the number in this register sets the decimation factor and thus the output update rate for the primary and auxiliary adcs. this sfr cannot be written by user software while either adc is active. the update rate applies to both primary and a uxiliary adcs and is calculated as follows: f sf f adc mod = 1 3 1 8. where: f adc = adc output update rate f mod = modulator clock frequency = 32.768 khz sf = decimal value of sf register the allowable range for sf is 0dhex to ffhex. examples of sf values and corresponding conversion update rate (f adc ) and con- version time (t adc ) are shown in table vii, the power-on default value for the sf register is 45 hex, resulting in a default adc update rate of just under 20 hz. both adc inputs are chopped to minimize offset errors, which means that the settling time for a single conversion or the time to a first conversion result in continuous conversion mode is 2 t adc . as mentioned earlier, all calibration cycles will be carried out automatically with a maximum, i.e., ffhex, sf value to ensure optimum calibra- tion performance. once a calibration cycle has completed, the value in the sf register will be that programmed by user software. table vii. sf sfr bit designations sf(dec) sf(hex) f adc (hz) t adc (ms) 13 0d 105.3 9.52 69 45 19.79 50.34 255 ff 5.35 186.77
rev. 0 ADUC816 C29C icon (current sources control register) used to control and configure the various excitation and burnout current source options available on-chip. sfr address d5h power-on default value 00h bit addressable no - - -o bc i 1 c d ac i 0 c d an i p 2 in i p 1 in e 2 in e 1 i table viii. icon sfr bit designations bit name description 7 --- reserved for future use. 6 bo burnout current enable bit. set by user to enable both transducer burnout current sources in the primary adc signal paths. cleared by user to disable both transducer burnout current sources. 5 adc1ic auxiliary adc current correction bit. set by user to allow scaling of the auxiliary adc by an internal current source calibration word. 4 adc0ic primary adc current correction bit. set by user to allow scaling of the primary adc by an internal current source calibration word. 3 i2pin * current source-2 pin select bit. set by user to enable current source-2 (200 a) to external pin 3 (p1.2/dac/iexc1). cleared by user to enable current source-2 (200 a) to external pin 4 (p1.3/ain5/iexc2). 2 i1pin * current source-1 pin select bit. set by user to enable current source-1 (200 a) to external pin 4 (p1.3/ain5/iexc2). cleared by user to enable current source-1 (200 a) to external pin 3 (p1.2/dac/iexc1). 1 i2en current source-2 enable bit. set by user to turn on excitation current source-2 (200 a). cleared by user to turn off excitation current source-2 (200 a). 0 i1en current source-1 enable bit. set by user to turn on excitation current source-1 (200 a). cleared by user to turn off excitation current source-1 (200 a). * both current sources can be enabled to the same external pin, yielding a 400 a current source. adc0h/adc0m (primary adc conversion result registers) these two 8-bit registers hold the 16-bit conversion result from the primary adc. sfr address adc0h high data byte dbh adc0m middle data byte dah power-on default value 00h both registers bit addressable no both registers adc1h/adc1l (auxiliary adc conversion result registers) these two 8-bit registers hold the 16-bit conversion result from the auxiliary adc. sfr address adc1h high data byte ddh adc1l low data byte dch power-on default value 00h both registers bit addressable no both registers
rev. 0 ADUC816 C30C of0h/of0m (primary adc offset calibration registers 1 ) these two 8-bit registers hold the 16-bit offset calibration coefficient for the primary adc. these registers are configured at power- on with a factory default value of 8000hex. however, these bytes will be automatically overwritten if an internal or system zer o-scale calibration is initiated by the user via md2 0 bits in the adcmode register. sfr address of0h primary adc offset coefficient high byte e3h of0m primary adc offset coefficient middle byte e2h power-on default value 8000h of0h and of0m respectively bit addressable no both registers of1h/of1l (auxiliary adc offset calibration registers 1 ) these two 8-bit registers hold the 16-bit offset calibration coefficient for the auxiliary adc. these registers are config ured at power-on with a factory default value of 8000hex. however, these bytes will be automatically overwritten if an internal or system zero-scale calibration is initiated by the user via the md2 0 bits in the adcmode register. sfr address of1h auxiliary adc offset coefficient high byte e5h of1l auxiliary adc offset coefficient low byte e4h power-on default value 8000h of1h and of1l respectively bit addressable no both registers gn0h/gn0m (primary adc gain calibration registers 1 ) these two 8-bit registers hold the 16-bit gain calibration coefficient for the primary adc. these registers are configured at p ower-on with a factory-calculated internal full-scale calibration coefficient. every device will have an individual coefficient. howeve r, these bytes will be automatically overwritten if an internal or system full-scale calibration is initiated by the user via md2 0 bits in the adcmode register. sfr address gn0h primary adc gain coefficient high byte ebh gn0m primary adc gain coefficient middle byte eah power-on default value configured at factory final test, see notes above. bit addressable no both registers gn1h/gn1l (auxiliary adc gain calibration registers 1 ) these two 8-bit registers hold the 16-bit gain calibration coefficient for the auxiliary adc. these registers are configured at power- on with a factory calculated internal full-scale calibration coefficient. every device will have an individual coefficient. how ever, these bytes will be automatically overwritten if an internal or system full-scale calibration is initiated by the user via md2 0 bits in the adcmode register. sfr address gn1h auxiliary adc gain coefficient high byte edh gn1l auxiliary adc gain coefficient low byte ech power-on default value configured at factory final test, see notes above. bit addressable no both registers note 1 these registers can be overwritten by user software only if mode bits md0 2 (adcmode sfr) are zero.
rev. 0 ADUC816 C31C primary and auxiliary adc circuit description overview the ADUC816 incorporates two independent sigma-delta adcs (primary and auxiliary) with on-chip digital filtering intended for the measurement of wide dynamic range, low frequency signals such as those in weigh-scale, strain-gauge, pressure trans- ducer or temperature measurement applications. primary adc this adc is intended to convert the primary sensor input. the input is buffered and can be programmed for one of 8 input ranges from 20 mv to 2.56 v being driven from one of three differ- ential input channel options ain1/2, ain3/4, or ain3/2. the input channel is internally buffered allowing the part to handle significant source impedances on the analog input, allowing r/c filtering (for noise rejection or rfi reduction) to be placed on sigma- delta modulator programmable digital filter sigma-delta a/d converter buffer agnd av dd refin( ) refin(+) programmable gain amplifier the programmable gain amplifier allows eight unipolar and eight bipolar input ranges from 20mv to 2.56v (ext vref = +2.5v) the modulator provides a high-frequency 1-bit data stream (the output of which is also chopped) to the digital filter, the duty cycle of which represents the sampled analog input voltage sigma-delta modulator chop analog input chopping the inputs are alternately reversed through the conversion cycle. chopping yields excellent adc offset and offset drift performance output average as part of the chopping implementation, each data word output from the filter is summed and averaged with its predecessor to null adc channel offset errors ain1 ain2 ain3 ain4 buffer amplifier the buffer amplifier presents a high impedance input stage for the analog inputs, allowing significant external source impedances burnout currents two 100na burnout currents allow the user to easily detect if a transducer has burned out or gone open-circuit programmable digital filter the sinc 3 filter removes quantization noise introduced by the modulator. the update rate and bandwidth of this filter are programmable via the sf sfr the ouput word from the digital filter is scaled by the calibration coefficients before being provided as the conversion result output scaling analog multiplexer a differential multiplexer allows selection of three fully differential pair options and additional internal short option (ain2 ain2).the multiplexer is controlled via the channel selection bits in adc0con sigma-delta adc the sigma-delta architecture ensures 16 bits no missing codes. the entire sigma-delta adc is chopped to remove drift error output average output scaling digtal output result written to adc0h/m sfrs pga differential reference the external reference input to the ADUC816 is differential and facilitates ratiometric operation. the external reference voltage is selected via the xref0 bit in adc0con. reference detect circuitry tests for open or shorted references inputs chop mux see page 36 see page 29 and 34 see page 34 see page 35 see page 35 see page 36 see page 37 see page 35 see page 35 see page 33 see pages 27 and 33 figure 18. primary adc block diagram the analog inputs if required. on-chip burnout currents can also be turned on. these currents can be used to check that a transducer on the selected channel is still operational before attempting to take measurements. the adc employs a sigma-delta conversion technique to realize up to 16 bits of no missing codes performance. the sigma-delta modulator converts the sampled input signal into a digital pulse train whose duty cycle contains the digital information. a sinc3 programmable low-pass filter is then employed to decimate the modulator output data stream to give a valid data conversion result at programmable output rates from 5.35 hz (186.77 ms) to 105.03 hz (9.52 ms). a chopping scheme is also employed to minimize adc offset errors. a block diagram of the primary adc is shown in figure 18.
rev. 0 ADUC816 C32C auxiliary adc the auxiliary adc is intended to convert supplementary inputs such as those from a cold junction diode or thermistor. this adc is not buffered and has a fixed input range of 0 v to 2.5 v mu x ain3 ain4 ain5 on-chip temperature sensor sigma- delta modulator programmable digital filter sigma-delta a/d converter refin( ) refin(+) chop output average output scaling digtal output result written to adc1h/l sfrs chop differential reference the external reference input to the ADUC816 is differential and facilitates ratiometric operation. the external refer- ence voltage is selected via the xref1 bit in adc1con. reference detect circuitry tests for open or shorted references inputs see page 35 the modulator provides a high frequency 1-bit data stream (the output of which is also chopped) to the digital filter, the duty cycle of which represents the sampled analog input voltage sigma-delta modulator see page 35 programmable digital filter the sinc 3 filter removes quantization noise introduced by the modulator. the update rate and bandwidth of this filter are programmable via the sf sfr see page 35 output average as part of the chopping implementation each data word output from the filter is summed and averaged with its predecessor to null adc channel offset errors see page 36 sigma-delta adc the sigma-delta architecture ensures 16 bits no missing codes. the entire sigma-delta adc is chopped to remove drift errors see page 35 the ouput word from the digital filter is scaled by the calibration coefficients before being provided as the conversion result output scaling see page 37 analog input chopping the inputs are alternately reversed through the conversion cycle. chopping yields excellent adc offset and offset drift performance see page 36 analog multiplexer a differential multiplexer allows selection of three external single ended inputs or the on-chip temp. sensor. the multiplexer is controlled via the channel selection bits in adc1con see page 28 and 33 mux figure 19. auxiliary adc block diagram (assuming an external 2.5 v reference). the single-ended inputs can be driven from ain3, ain4 or ain5 pins or directly from the on-chip temperature sensor voltage. a block diagram of the auxiliary adc is shown in figure 19.
rev. 0 ADUC816 C33C table ix. primary adc, typical output rms noise ( v) typical output rms noise vs. input range and update rate; output rms noise in v sf data update input range word rate (hz) 20 mv 40 mv 80 mv 160 mv 320 mv 640 mv 1.28 v 2.56 v 13 105.3 1.50 1.50 1.60 1.75 3.50 4.50 6.70 11.75 69 19.79 0.60 0.65 0.65 0.65 0.65 0.95 1.40 2.30 255 5.35 0.35 0.35 0.37 0.37 0.37 0.51 0.82 1.25 table x. primary adc, peak-to-peak resolution (bits) peak-to-peak resolution vs. input range and update rate; peak-to-peak resolution in bits sf data update input range word rate (hz) 20 mv 40 mv 80 mv 160 mv 320 mv 640 mv 1.28 v 2.56 v 13 105.3 12 13 14 15 15 15.5 16 16 69 19.79 13 14 15 16 16 1 16 1 16 1 16 1 255 5.35 14 15 16 16 1 16 1 16 1 16 1 16 1 note 1 peak-to-peak resolution at these range/update rate settings is limited only by the number of bits available from the adc. effec tive resolution at these range/update rate settings is greater than 16 bits as indicated by the rms noise table shown in table ix. table xi. auxiliary adc typical output rms noise vs. update rate 1 output rms noise in v sf data update input range word rate (hz) 2.5 v 13 105.3 10.75 69 19.79 2.00 255 5.35 1.15 note 1 adc converting in bipolar mode. peak-to-peak resolution vs. update rate 1 peak-to-peak resolution in bits sf data update input range word rate (hz) 2.5 v 13 105.3 16 2 69 19.79 16 255 5.35 16 notes 1 adc converting in bipolar mode. 2 in unipolar mode peak-to-peak resolution at 105 hz is 15 bits. analog input channels the primary adc has four associated analog input pins (labelled ain1 to ain4) which can be configured as two fully differential input channels. channel selection bits in the adc0con sfr detailed in table v allow three combinations of differential pair selection as well as an additional shorted input o ption (ain2?in2). the auxiliary adc has three external input pins (labelled ain3 to ain5) as well as an internal connection to the internal on-chip temperature sensor. all inputs to the auxiliary adc are single- ended inputs referenced to the agnd on the part. channel selection bits in the adc1con sfr detailed previously in table vi allow selection of one of four inputs. two input multiplexers switch the selected input channel to the on-chip buffer amplifier in the case of the primary adc and directly to the sigma-delta modulator input in the case of the auxiliary adc. when the analog input channel is switched, the settling time of the part must elapse before a new valid word is available from the adc. primary and auxiliary adc inputs the output of the primary adc multiplexer feeds into a high impedance input stage of the buffer amplifier. as a result, the primary adc inputs can handle significant source impedances and are tailored for direct connection to external resistive -type sensors like strain gauges or resistance temperature detectors (rtds). the auxiliary adc, however, is unbuffered resulting in higher analog input current on the auxiliary adc. it should be noted that this unbuffered input path provides a dynamic load to the driving source. therefore, resistor/capacitor combinations on the input pins can cause dc gain errors depending on the output imped ance of the source that is driving the adc inputs. analog input ranges the absolute input voltage range on the primary adc is re stricted to between agnd + 100 mv to avdd 100 mv. care must be taken in setting up the common-mode voltage and input voltage range so that these limits are not exceeded, otherwise there will be a degradation in linearity performance. primary and auxiliary adc noise performance tables ix, x and xi below show the output rms noise in v and output peak-to-peak resolution in bits (rounded to the nearest 0.5 lsb) for some typical output update rates on both the primary and auxiliary adcs. the numbers are typical and are generated at a differential input voltage of 0 v. the output update rate is selected via the sf7?f0 bits in the sinc filter (sf) sfr. it is important to note that the peak-to-peak resolu- tion figures represent the resolution for which there will be no code flicker within a six-sigma limit.
rev. 0 ADUC816 C34C the absolute input voltage range on the auxiliary adc is re stricted to between agnd ?30 mv to avdd + 30 mv. the slightly negative absolute input voltage limit does allow the possibility of monitoring small signal bipolar signals using the single-ended auxiliary adc front end. programmable gain amplifier the output from the buffer on the primary adc is applied to the input of the on-chip programmable gain amplifier (pga). the pga can be programmed through eight different unipolar input ranges and bipolar ranges. the pga gain range is programmed via the range bits in the adc0con sfr. with the external refer- ence select bit set in the adc0con sfr and an external 2.5 v reference, the unipolar ranges are 0 mv to +20 mv, 0 mv to 40 mv, 0 mv to 80 mv, 0 mv to 160 mv, 0 mv to 320 mv, 0 mv to 640 mv and 0 v to 1.28 v and 0 to 2.56 v while the bipolar ranges are 20 mv, 40 mv, 80 mv, 160 mv, 320 mv, 640 mv, 1.28 v and 2.56 v. these are the nominal ranges that should appear at the input to the on-chip pga. an adc range matching specification of 0.5 lsb (typ) across all ranges means that calibration need only be carried out at a single gain range and does not have to be repeated when the pga gain range is changed. the auxiliary adc does not incorporate a pga and is configured for a fixed single input range of 0 to v ref . bipolar/unipolar inputs the analog inputs on the ADUC816 can accept either uni- polar or bipolar input voltage ranges. bipolar input ranges do not imply that the part can handle negative voltages with respect to system agnd. unipolar and bipolar signals on the ain(+) input on the primary adc are referenced to the voltage on the respective ain(? input. for example, if ain(? is 2.5 v and the primary adc is config- ured for an analog input range of 0 mv to +20 mv, the input voltage range on the ain(+) input is 2.5 v to 2.52 v. if ain(? is 2.5 v and the ADUC816 is configured for an analog input range of 1.28 v, the analog input range on the ain(+) input is 1.22 v to 3.78 v (i.e., 2.5 v 1.28 v). as mentioned earlier, the auxiliary adc input is a single-ended input with respect to the system agnd. in this context a bipolar signal on the auxiliary adc can only span 30 mv negative with respect to agnd before violating the voltage input limits for this adc. bipolar or unipolar options are chosen by programming the primary and auxiliary unipolar enable bits in the adc0con and adc1con sfrs respectively. this programs the relevant adc for either unipolar or bipolar operation. programming for either unipolar or bipolar operation does not change any of the input signal conditioning; it simply changes the data output coding and the points on the transfer function where calibrations occur. when an adc is configured for unipolar operation, the output coding is natural (straight) binary with a zero differential input voltage resulting in a code of 000 . . . 000, a midscale voltage resulting in a code of 100 . . . 000, and a full-scale input voltage resulting in a code of 111 . . . 111. when an adc is configured for bipolar operation, the coding is offset binary with a negative full-scale voltage resulting in a code of 000 . . . 000, a zero differential voltage resulting in a code of 100 . . . 000, and a positive full-scale voltage resulting in a code of 111 . . . 111. burnout currents the primary adc on the ADUC816 contains two 100 na con- stant current generators, one sourcing current from avdd to ain(+), and one sinking from ain(? to agnd. the currents are switched to the selected analog input pair. both currents are either on or off, depending on the burnout current enable (bo) bit in the icon sfr (see table viii). these currents can be used to verify that an external transducer is still operational before attempting to take measurements on that channel. once the burnout currents are turned on, they will flow in the exter- nal transducer circu it, and a measurement of the input voltage on the analog input channel can be taken. if the resultant volt- age measured is full-scale, this indicates that the transducer has gone open-circuit. if the voltage measured is 0 v, it indicates that the transducer has short circuited. for normal operation, these burnout currents are turned off by w riting a 0 to the bo bit in the icon sfr. the current sources work over the normal abso- lute input voltage range specifications. excitation currents the ADUC816 also contains two identical, 200 a constant current sources. both source current from avdd to pin 3 (iexc1) or pin 4 (iexc2) these current sources are con- trolled via bits in the icon sfr shown in table viii. they can be configured to source 200 a individually to both pins or a combination of both currents, i.e., 400 a to either of the selected pins. these current sources can be used to excite exter- nal resistive bridge or rtd sensors. reference input the ADUC816? reference inputs, refin(+) and refin(?, provide a differential reference input capability. the common- mode range for these differential inputs is from agnd to avdd. the nominal reference voltage, vref (refin(+) ?refin()), for specified operation is 2.5 v with the primary and auxil- iary reference enable bits set in the respective adc0con and/or adc1con sfrs. the part is also functional (although not specified for perfor- mance) when the xref0 or xref1 bits are ?,?which enables the on-chip internal bandgap reference. in this mode, the adcs will see the internal reference of 1.25 v, therefore halving all input ranges. as a result of using the internal reference volt- age, a noticeable degradation in peak-to-peak resolution will result. therefore, for best performance, operation with an exter- nal reference is strongly recommended. in applications where the excitation (voltage or current) for the transducer on the analog input also drives the reference voltage for the part, the effect of the low-frequency noise in the excita- tion source will be removed as the application is ratiometric. if the ADUC816 is not used in a ratiometric application, a low noise reference should be used. recommended reference voltage sources for the ADUC816 include the ad780, ref43, and ref192. it should also be noted that the reference inputs provide a high impedance, dynamic load. because the input impedance of each reference input is dynamic, resistor/capacitor combinations on these inputs can cause dc gain errors depending on the output impedance of the source that is driving the reference inputs. reference voltage sources, like those recommended above (e.g., ad780) will typically have low output impedances and therefore decoupling capacitors on the refin(+) input would be recom-
rev. 0 ADUC816 C35C mended. deriving the reference input voltage across an external resistor, as shown in figure 52, will mean that the reference input sees a significant external source impedance. external decoupling on the refin(+) and refin (? pins would not be recommended in this type of circuit configu ration. reference detect the ADUC816 includes on-chip circuitry to detect if the part has a valid reference for conversions or calibrations. if the voltage between the external refin(+) and refin(? pins goes below 0.3 v or either the refin(+) or refin(? inputs is open circuit, the ADUC816 detects that it no longer has a valid reference. in this case, the noxref bit of the adcstat sfr is set to a 1. if the ADUC816 is performing normal conversions and the noxref bit becomes active, the conversion results revert to all 1s. therefore, it is not necessary to continuously monitor the status of the noxref bit when performing conversions. it is only necessary to verify its status if the conversion result read from the adc data register is all 1s. if the ADUC816 is performing either an offset or gain calibration and the noxref bit becomes active, the updating of the respec- tive calibration registers is inhibited to avoid loading incorrect coefficients to these registers, and the appropriate err0 or err1 bits in the adcstat sfr are set. if the user is concerned about verifying that a valid reference is in place every time a cali- bration is performed, the status of the err0 or err1 bit should be checked at the end of the calibration cycle. sigma-delta modulator a sigma-delta adc generally consists of two main blocks, an analog modulator and a digital filter. in the case of the ADUC816 adcs, the analog modulators consist of a difference amplifier, an integrator block, a comparator, and a feedback dac as illus- trated in figure 20. dac integrator analog input difference amp comparator high- frequency bitstream to digital filter figure 20. sigma-delta modulator simplified block diagram in operation, the analog signal sample is fed to the difference amplifier along with the output of the feedback dac. the differ- ence between these two signals is integrated and fed to the comparator. the output of the comparator provides the input to the feedback dac so the system functions as a negative feedback loop that tries to minimize the difference signal. the digital data that represents the analog input voltage is contained in the duty cycle of the pulse train appearing at the output of the comparator. this duty cycle data can be recovered as a data word using a subsequent digital filter stage. the sampling frequency of the modulator loop is many times higher than the bandwidth of the input signal. the integrator in the modulator shapes the quantization noise (which results from the analog-to-digital con- version) so that the noise is pushed toward one-half of the modulator frequency. digital filter the output of the sigma-delta modulator feeds directly into the digital filter. the digital filter then band-limits the response to a frequency significantly lower than one-half of the modulator frequency. in this manner, the 1-bit output of the comparator is translated into a band-limited, low noise output from the ADUC816 adcs. the ADUC816 filter is a low-pass, sinc 3 or (sinx/x) 3 filter whose primary function is to remove the quantization noise introduced at the modulator. the cutoff frequency and decimated output data rate of the filter are programmable via the sf (sinc filter) sfr as described in table vii. figure 21 shows the frequency response of the adc chan- nel at the default sf word of 69 dec or 45 hex, yielding an overall output update rate of just under 20 hz. it should be noted that this frequency response allows frequency components higher than the adc nyquist frequency to pass through the adc, in some cases without significant attenuation. these components may, therefore, be aliased and appear in-band after the sampling process. it should also be noted that rejection of mains-related frequency components, i.e., 50 hz and 60 hz, is seen to be at level of >65 db at 50 hz and >100 db at 60 hz. this confirms the data sheet specifications for 50 hz/60 hz normal mode rejec- tion (nmr) at a 20 hz update rate. 0 20 30 50 70 80 90 100 110 frequency ?hz gain ?db 0 ?0 ?0 ?0 ?0 ?0 ?00 ?10 ?20 10 40 60 ?0 ?0 ?0 ?0 figure 21. filter response, sf = 69 dec the response of the filter, however, will change with sf word as can be seen in figure 22, which shows >90 db nmr at 50 hz and >70 db nmr at 60 hz when sf = 255 dec. 0203050708090 100 frequency hz gain db 0 20 40 70 80 90 100 110 120 10 40 60 10 30 60 50 figure 22. filter response, sf = 255 dec
rev. 0 ADUC816 C36C figures 23 and 24 show the nmr for 50 hz and 60 hz across the full range of sf word, i.e., sf = 13 dec to sf = 255 dec. 10 50 70 110 150 170 190 210 sf decimal gain db 0 20 40 70 80 90 100 110 120 30 90 130 10 30 60 50 230 250 figure 23. 50 hz normal mode rejection vs. sf 10 50 70 110 150 170 190 210 sf decimal gain db 0 20 40 70 80 90 100 110 120 30 90 130 10 30 60 50 230 250 figure 24. 60 hz normal mode rejection vs. sf adc chopping both adcs on the ADUC816 implement a chopping scheme whereby the adc repeatability reverses its inputs. the deci- mated digital output words from the sinc 3 filters therefore have a positive offset and negative offset term included. as a result, a final summing stage is included in each adc so that each output word from the filter is summed and averaged with the previous filter output to produce a new valid output result to be written to the adc data sfrs. in this way, while the adc throughput or update rate is as discussed earlier and illustrated in table vii, the full settling time through the adc (or the time to a first conversion result), will actually be given by 2 t adc . the chopping scheme incorporated in the ADUC816 adc results in excellent dc offset and offset drift specifications and is extremely beneficial in applications where drift, noise rejection, and optimum emi rejection are important factors. calibration the ADUC816 provides four calibration modes that can be pro- grammed via the mode bits in the adcmode sfr detailed in table iv. in fact, every ADUC816 has already been factory calibrated. the resultant offset and gain calibration coefficients for both the primary and auxiliary adcs are stored on-chip in manufacturing-specific flash/ee memory locations. at power- on, these factory calibration coefficients are automatically downloaded to the calibration registers in the ADUC816 sfr space. each adc (primary and auxiliary) has dedicated calibration sfrs, these have been described earlier as part of the general adc sfr description. however, the factory calibration values in the adc calibration sfrs will be overwritten if any one of the four calibration options are initiated and that adc is en abled via the adc enable bits in adcmode. even though an internal offset calibration mode is described below, it should be recognized that both adcs are chopped. this chopping scheme inherently minimizes offset and means that an internal offset calibration should never be required. also, because factory 5 v/25 c gain calibration coefficients are automatically present at power-on, an internal full-scale calibration will only be required if the part is being operated at 3 v or at tempera tures significantly different from 25 c. the ADUC816 offers ?nternal?or ?ystem?calibration facilities. for full calibration to occur on the selected adc, the calibration logic must record the modulator output for two different input conditions. these are ?ero-scale?and ?ull-scale?points. these points are derived by performing a conversion on the different input voltages provided to the input of the modulator during calibration. the result of the ?ero-scale?calibration conversion is stored in the offset calibration registers for the appropri- ate adc. the result of the ?ull-scale?calibration conversion is stored in the gain calibration registers for the appropriate adc. with these readings, the calibration logic can calculate the offset and the gain slope for the input-to-output transfer function of the converter. during an ?nternal?zero-scale or full-scale calibration, the respective ?ero?input and ?ull-scale?input are automatically connected to the adc input pins internally to the device. a ?ystem?calibration, however, expects the system zero-scale and system full-scale voltages to be applied to the external adc pins before the calibration mode is initiated. in this way external adc errors are taken into account and minimized as a result of system calibration. it should also be noted that to optimize calibration accuracy, all ADUC816 adc calibrations are carried out auto- matically at the slowest update rate. internally in the ADUC816, the coefficients are normalized before being used to scale the words coming out of the digital filter. the offset calibration coefficient is subtracted from the result prior to the multiplication by the gain coefficient. all ADUC816 adc specifications will only apply after a zero-scale and full-scale calibration at the operating point (supply voltage/temperature) of interest. from an operational point of view, a calibration should be treated like another adc conversion. a zero-scale calibration (if requ ired) should always be carried out before a full-scale calibration. s ystem software should monitor the relevant adc rdy0/1 bit in the adcstat sfr to determine end of calibration via a polling sequence or interrupt driven routine.
rev. 0 ADUC816 C37C nonvolatile flash/ee memory flash/ee memory overview the ADUC816 incorporates flash/ee memory technology on-chip to provide the user with nonvolatile, in-circuit rep rogrammable, code and data memory space. flash/ee memory is a relatively recent type of nonvolatile me mory technology and is based on a single transistor cell architecture. this technology is basically an outgrowth of eprom technology and was developed through the late 1980s. flash/ee memory takes the flexible in-circuit reprogrammable features of eeprom and combines them with the space efficient/density features of eprom (see figure 25). because flash/ee technology is based on a single transistor cell architecture, a flash memory array, like eprom, can be imple- mented to achieve the space efficiencies or memory densities required by a given design. like eeprom, flash memory can be programmed in-system at a byte level, although it must first be erased; the erase being per- formed in page blocks. thus, flash memory is often and more correctly referred to as flash/ee memory. flash/ee memory technology space efficient/ density in-circuit reprogrammable eprom technology eeprom technology figure 25. flash/ee memory development overall, flash/ee memory represents a step closer to the ideal memory device that includes nonvolatility, in-circuit program- mability, high density and low cost. incorporated in the aduc 816, flash/ee memory technology allows the user to update program code space in-circuit, without the need to replace one-time programmable (otp) devices at remote operating nodes. flash/ee memory and the ADUC816 the ADUC816 provides two arrays of flash/ee memory for user applications. 8k bytes of flash/ee program space are provided on-chip to facilitate code execution without any external discrete rom device requirements. the program memory can be pro- grammed using conventional third party memory programmers. this array can also be programmed in-circuit, using the serial download mode provided. a 640-byte flash/ee data memory space is also provided on- chip. this may be used as a general-purpose nonvolatile scratchpad area. user access to this area is via a group of six sfrs. this space can be programmed at a byte level, although it must first be erased in 4-byte pages. ADUC816 flash/ee memory reliability the flash/ee program and data memory arrays on the ADUC816 are fully qualified for two key flash/ee memory characteristics, namely flash/ee memory cycling endurance and flash/ee memory data retention. endurance quantifies the ability of the flash/ee memory to be cycled through many program, read, and erase cycles. in real terms, a single endurance cycle is composed of four independent, sequential events. these events are defined as: a. initial page erase sequence b. read/verify sequence a single flash/ee c. byte program sequence memory d. second read/verify sequence endurance cycle in reliability qualification, every byte in both the program and data flash/ee memory is cycled from 00 hex to ffhex until a first fail is recorded signifying the endurance limit of the on-chip flash/ee memory. as indicated in the specification pages of this data sheet, the ADUC816 flash/ee memory endurance qualification has been carried out in accordance with jedec specification a117 over the industrial temperature range of ?0 c, +25 c, and +85 c. the results allow the specification of a minimum endurance figure over supply and temperature of 100,000 cycles, with an endur ance figure of 700,000 cycles being typical of operation at 25 c. retention quantifies the ability of the flash/ee memory to retain its programmed data over time. again, the ADUC816 has been qualified in accordance with the formal jedec retention life- time specification (a117) at a specific junction temperature (t j = 55 c). as part of this qualification procedure, the flash/ee memory is cycled to its specified endurance limit described above, before data retention is characterized. this means that the flash/ ee memory is guaranteed to retain its data for its full specified retention lifetime every time the flash/ee memory is repro- grammed. it should also be noted that retention lifetime, based on an activation energy of 0.6 ev, will derate with t j as shown in figure 26. 40 60 70 90 t j junction temperature c retention years 250 200 150 100 50 0 50 80 110 300 100 adi specification 100 years min. at t j = 55 c figure 26. flash/ee memory data retention
rev. 0 ADUC816 C38C using the flash/ee program memory the 8 kbyte flash/ee program memory array is mapped into the lower 8 kbytes of the 64 kbytes program space addressable by the ADUC816, and is used to hold user code in typical applications. the program memory flash/ee memory arrays can be pro- grammed in one of two modes, namely: serial downloading (in-circuit programming) as part of its factory boot code, the ADUC816 facilitates serial code download via the standard uart serial port. serial down load mode is automatically entered on power-up if the external pin, psen , is pulled low through an external resistor as shown in figure 27. once in this mode, the user can download code to the program memory array while the device is sited in its target application hardware. a pc serial download executable is provided as part of the ADUC816 quickstart devel- opment system. the serial download protocol is detailed in a microconverter applications note uc004 available from the adi microconverter website at www.analog.com/microconverter. psen ADUC816 pull psen low during reset to configure the ADUC816 for serial download mode 1k figure 27. flash/ee memory serial download mode programming parallel programming the parallel programming mode is fully compatible with conven- tional third party flash or eeprom device programmers. a block diagram of the external pin configuration required to support parallel programming is shown in figure 28. in this mode, ports 0, 1, and 2 ope rate as the external data and ad dress bus inter face, ale operates as the write enable strobe, and port 3 is used as a general configuration port that configures the device for various program and erase operations during parallel programming. the high voltage (12 v) supply required for flash/ee program- ming is generated using on-chip charge pumps to supply the high voltage program lines. v dd gnd p3 psen reset p0 p1 p2 ale ADUC816 5v program mode (see table xii) gnd program data (d0 d7) program address (a0 a13) (p2.0 = a0) (p1.7 = a13) write enable strobe command enable p3.0 negative edge p3.6 entry sequence v dd figure 28. flash/ee memory parallel programming table xii. flash/ee memory parallel programming modes port 3 pins programming 0.7 0.6 0.5 0.4 0.3 0.2 0.1 mode xxxx 000e rase flash/ee program, data, and security modes xxxx 001r ead device signature/id xxx1010p rogram code byte xxx0010p rogram data byte xxx1011r ead code byte xxx0011r ead data byte xxxx 100p rogram security modes xxxx 101r ead/verify security modes all other codes redundant flash/ee program memory security the ADUC816 facilitates three modes of flash/ee program memory security. these modes can be independently activated, restricting access to the internal code space. these security modes can be enabled as part of the user interface available on all ADUC816 serial or parallel programming tools referenced on the microconverter web page at www.analog.com/microconverter. the security modes available on the ADUC816 are described as follows: lock mode this mode locks code in memory, disabling parallel program- ming of the program memory although reading the memory in parallel mode is still allowed. this mode is deactivated by initi- ating a ?ode-erase?command in serial download or parallel programming modes. secure mode this mode locks code in memory, disabling parallel programming (program and verify/read commands) as well as disabling the execution of a movc instruction from external memory, which is attempting to read the op codes from internal memory. this mode is deactivated by initiating a ?ode-erase?command in serial download or parallel programming modes.
rev. 0 ADUC816 C39C serial safe mode this mode disables serial download capability on the device. if serial safe mode is activated and an attempt is made to reset the part into serial download mode, i.e., reset asserted and deasserted with psen low, the part will interpret the serial download reset as a normal reset only. it will, therefore, not enter serial download mode but only execute a normal reset sequence. serial safe mode can only be disabled by initiating a code-erase command in parallel programming mode. using the flash/ee data memory the user flash/ee data memory array consists of 640 bytes that are configured into 160 (00h to 9fh) 4-byte pages as shown in figure 29. 9fh byte 1 byte 2 byte 3 byte 4 00h byte 1 byte 2 byte 3 byte 4 figure 29. flash/ee data memory configuration as with other ADUC816 user-peripheral circuits, the interface to this memory space is via a group of registers mapped in the sfr space. a group of four data registers (edata1?) are used to hold 4-byte page data just accessed. eadrl is used to hold the 8-bit address of the page to be accessed. finally, econ is an 8- bit control register that may be written with one of five flash/ee memory access commands to trigger various read, write, erase, and verify functions. these registers can be summarized as follows: econ: sfr address: b9h function: controls access to 640 bytes flash/ee data space. default: 00h eadrl: sfr address: c6h function: holds the flash/ee data page address. (640 bytes => 160 page addresses.) default: 00h edata 1?: sfr address: bch to bfh respectively function: holds flash/ee data memory page write or page read data bytes. default : edata1? ? 00h edata3? ? 00h a block diagram of the sfr interface to the flash/ee data memory array is shown in figure 30. 9fh byte 1 byte 2 byte 3 byte 4 00h edata1 (byte 1) edata2 (byte 2) edata3 (byte 3) edata4 (byte 4) eadrl econ command interpreter logic econ byte 1 byte 2 byte 3 byte 4 function: receives command data function: holds the 8-bit page address pointer function: interprets the flash command word function: holds the 4-byte page data figure 30. fl ash/ee data memory control and configu ration econ?lash/ee memory control sfr this sfr acts as a command interpreter and may be written with one of five command modes to enable various read, program and erase cycles as detailed in table xiii: table xiii. econ?lash/ee memory control register command modes command byte command mode 01h read command. results in four bytes being read into edata14 from memory page address contained in eadrl. 02h program command. results in four bytes (edata1?) being written to memory page address in eadrl. this write command assumes the designated ?rite?page has been pre-erased. 03h reserved for internal use. 03h should not be written to the econ sfr. 04h verify command. allows the user to verify if data in edata1? is contained in page address designated by eadrl. a subsequent read of the econ sfr will result in a ?ero?being read if the verification is valid, a nonzero value will be read to indicate an inv alid verification. 05h erase command. results in an erase of the 4-byte page designated in eadrl. 06h erase-all command. results in erase of the full flash/ee data memory 160-page (640 bytes) array. 07h to ffh reserved commands. commands reserved for future use.
rev. 0 ADUC816 C40C flash/ee memory timing the typical program/erase times for the flash/ee data memory are: erase full array (640 bytes) ?2 ms erase single page (4 bytes) ?2 ms program page (4 bytes) ?250 s read page (4 bytes) ?within single instruction cycle using the flash/ee memory interface as with all flash/ee memory architectures, the array can be pro- grammed in-system at a byte level, although it must be erased first; the erasure being performed in page blocks (4-byte pages in this case). a typical access to the flash/ee data array will involve setting up the page address to be accessed in the eadrl sfr, config- uring the edata1? with data to be programmed to the array (the edata sfrs will not be written for read accesses) and finally, writing the econ command word which initiates one of the six modes shown in table xiii. it should be noted that a given mode of operation is initiated as soon as the command word is written to the econ sfr. the core microcontroller operation on the ADUC816 is idled until the requested program/read or erase mode is completed. in practice, this means that even though the flash/ee memory mode of operation is typically initiated with a two-machine cycle mov instruction (to write to the econ sfr), the next instruc- tion will not be executed until the flash/ee operation is complete (250 s or 2 ms later). this means that the core will not respond to interrupt requests until the flash/ee operation is complete, although the core peripheral functions like counter/timers will continue to count and time as configured throughout this period. erase-all although the 640-byte user flash/ee array is shipped from the factory pre-erased, i.e., byte locations set to ffh, it is nonethe- less good programming practice to include an erase-all routine as part of any configuration/setup code running on the ADUC816. an ?rase-all?command consists of writing ?6h?to the econ sfr, which initiates an erase of all 640 byte locations in the flash/ee array. this command coded in 8051 assembly would appear as: mov econ, #06h ; erase all command ; 2 ms duration program a byte in general terms, a byte in the flash/ee array can only be pro- grammed if it has previously been erased. to be more specific, a byte can only be programmed if it already holds the value ffh. because of the flash/ee architecture, this erasure must happen at a page level; therefore, a minimum of four bytes (1 page) will be erased when an erase command is initiated. a more specific example of the program-byte process is shown below. in this example the user writes f3h into the second byte on page 03h of the flash/ee data memory space while preserving the other three bytes already in this page. as the user is only required to modify one of the page bytes, the full page must be first read so that this page can then be erased without the exist- ing data being lost. this example, coded in 8051 assembly, would appear as: mov eadrl,#03h ; set page address pointer mov econ,#01h ; read page mov edata2,#0f3h ; write new byte mov econ,#05h ; erase page mov econ,#02h ; write page (program flash/ee)
rev. 0 ADUC816 C41C user interface to other on-chip ADUC816 peripherals the following section gives a brief overview of the various peripherals also available on-chip. a summary of the sfrs used to control and configure these peripherals is also given. dac the ADUC816 incorporates a 12-bit, voltage output dac on-chip. it has a rail-to-rail voltage output buffer capable of driving 10 k ? /100 pf. it has two selectable ranges, 0 v to v ref (the internal bandgap 2.5 v reference) and 0 v to av dd . it can operate in 12-bit or 8-bit mode. the dac has a control regis- ter, daccon, and two data registers, dach/l. the dac output can be programmed to appear at pin 3 or pin 12. it should be noted that in 12-bit mode, the dac voltage output will be updated as soon as the dacl data sfr has been writ- ten; therefore, the dac data registers should be updated as dach first followed by dacl. 5 daccon dac control register sfr address fdh power-on default value 00h bit addressable no - - -- - -- - -n i p c a d8 c a dn r c a d r l c c a d n e c a d table xiv. daccon sfr bit designations bit name description 7 --- reserved for future use. 6 --- reserved for future use. 5 --- reserved for future use. 4 dacpin dac output pin select. set by the user to direct the dac output to pin 12 (p1.7/ain4/dac). cleared by user to direct the dac output to pin 3 (p1.2/dac/iexc1). 3 dac8 dac 8-bit mode bit. set by user to enable 8-bit dac operation. in this mode the 8-bits in dacl sfr are routed to the 8 msbs of the dac and the 4 lsbs of the dac are set to zero. cleared by user to operate the dac in its normal 12-bit mode of operation. 2 dacrn dac output range bit. set by user to configure dac range of 0 ?av dd . cleared by user to configure dac range of 0 ?2.5 v. 1 dacclr dac clear bit. set to ??by user to enable normal dac operation. cleared to ??by user to reset dac data registers dacl/h to zero. 0 dacen dac enable bit. set to ??by user to enable normal dac operation. cleared to ??by user to power-down the dac. dach/l dac data registers function dac data registers, written by user to update the dac output. sfr address dacl (dac data low byte) ?fbh dach (dac data high byte) ?fch power-on default value 00h ?both registers bit addressable no ?both registers the 12-bit dac data should be written into dach/l right-justified such that dacl contains the lower eight bits, and the lower nibble of dach contains the upper four bits.
rev. 0 ADUC816 C42C on-chip pll the ADUC816 is intended for use with a 32.768 khz watch crys- tal. a pll locks onto a multiple (384) of this to provide a stable 12.582912 mhz clock for the system. the core can operate at this frequency or at binary submultiples of it to allow power saving in cases where maximum core performance is not required. the d efault core clock is the pll clock divided by 8 or 1.572864 mhz. the adc clocks are also derived from the pll clock, with the modulator rate being the same as the crystal oscillator frequency. the above choice of frequencies ensures that the m odulators and the core will be synchronous, regardless of the core clock rate. the pll con trol register is pllcon. pllcon pll control register sfr address d7h power-on default value 03h bit addressable no d p _ c s ok c o l- - - a e t l t n i f2 d c1 d c0 d c table xv. pllcon sfr bit designations bit name description 7 osc_pd oscillator power-down bit. set by user to halt the 32 khz oscillator in power-down mode. cleared by user to enable the 32 khz oscillator in power-down mode. this feature allows the tic to continue counting even in power-down mode. 6 lock pll lock bit. this is a read only bit. set automatically at power-on to indicate the pll loop is correctly tracking the crystal clock. if the external crystal becomes subsequently disconnected the pll will rail and the core will halt. cleared automatically at power-on to indicate the pll is not correctly tracking the crystal clock. this may be due to the absence of a crystal clock or an external crystal at power-on. in this mode, the pll output can be 12.58 mhz 20%. 5 --- reserved for future use; should be written with ?. 4 ltea reading this bit returns the state of the external ea pin latched at reset or power-on. 3 fint fast interrupt response bit. set by user enabling the response to any interrupt to be executed at the fastest core clock frequency, regardless of the configuration of the cd2? bits (see below). once user code has returned from an interrupt, the core resumes code execution at the core clock selected by the cd2? bits. cleared by user to disable the fast interrupt response feature. 2 cd2 cpu (core clock) divider bits. 1 cd1 this number determines the frequency at which the microcontroller core will operate. 0 cd0 cd2 cd1 cd0 core clock frequency (mhz) 0 0 0 12.582912 0 0 1 6.291456 0 1 0 3.145728 0 1 1 1.572864 (default core clock frequency) 1 0 0 0.786432 1 0 1 0.393216 1 1 0 0.196608 1 1 1 0.098304
rev. 0 ADUC816 C43C time interval counter (tic) a time interval counter is provided on-chip for counting longer intervals than the standard 8051-compatible timers are capable of. the tic is capable of timeout intervals ranging from 1/128th second to 255 hours. furthermore, this counter is clocked by the crystal oscillator rather than the pll and thus has the ability to remain active in power-down mode and time long power-down intervals. this has obvious applications for remote battery-powered sensors where regular widely spaced readings are required. six sfrs are associated with the time interval counter, ti mecon being its control register. depending on the configuration of the it0 and it1 bits in timecon, the selected time counter register overflow will clock the interval counter. when this counter is equal to the time interval value loaded in the intval sfr, the tii bit (timecon.2) is set and generates an interrupt if enabled (see ieip2 sfr description under interrupt system later in this data sheet.) if the ADUC816 is in power-down mode, again with tic interrupt enabled, the tii bit will wake up the device and resume code execution by vectoring directly to the tic interrupt service vector address at 0053 hex. the tic-related sfrs are described in table xvi. note also that the timebase sfrs can be written initially with the current time, the tic can then be controlled and accessed by user software. in effect, this facilitates the implem enta tion of a real-time clock. a block diagram of the tic is shown in figure 31. 8-bit prescaler hundredths counter hthsec second counter sec minute counter min hour counter hour tien interval timeout time interval counter interrupt 8-bit interval counter time interval intval interval timebase selection mux tcen 32.768khz external crystal its0, 1 compare count = intval? figure 31. tic, simplified block diagram
rev. 0 ADUC816 C44C timecon tic control register sfr address a1h power-on default value 00h bit addressable no - - -- - -1 s t i0 s t ii t si i tn e i tn e c t table xvi. timecon sfr bit designations bit name description 7 --- reserved for future use. 6 --- reserved for future use. for future product code compatibility this bit should be written as a ?. 5 its1 interval timebase selection bits. 4 its0 written by user to determine the interval counter update rate. its1 its0 interval timebase 0 0 1/128 second 0 1 seconds 1 0 minutes 1 1 hours 3 sti single time interval bit. set by user to generate a single interval timeout. if set, a timeout will clear the tien bit. cleared by user to allow the interval counter to be automatically reloaded and start counting again at each interval timeout. 2 tii tic interrupt bit. set when the 8-bit interval counter matches the value in the intval sfr. cleared by user software. 1 tien time interval enable bit. set by user to enable the 8-bit time interval counter. cleared by user to disable and clear the contents of the interval counter. 0 tcen time clock enable bit. set by user to enable the time clock to the time interval counters. cleared by user to disable the clock to the time interval counters and clear the time interval sfrs. the time registers (hthsec, sec, min and hour) can be written while tcen is low.
rev. 0 ADUC816 C45C intval user time interval select register function user code writes the required time interval to this register. when the 8-bit interval counter is equal to the time interval value loaded in the intval sfr, the tii bit (timecon.2) bit is set and generates an interrupt if enabled. (see ieip2 sfr description under interrupt system later in this data sheet.) sfr address a6h power-on default value 00h bit addressable no valid value 0 to 255 decimal hthsec hundredths seconds time register function this register is incremented in (1/128) second intervals once tcen in timecon is active. the hthsec sfr counts from 0 to 127 before rolling over to increment the sec time register. sfr address a2h power-on default value 00h bit addressable no valid value 0 to 127 decimal sec seconds time register function this register is incremented in 1-second intervals once tcen in timecon is active. the sec sfr counts from 0 to 59 before rolling over to increment the min time register. sfr address a3h power-on default value 00h bit addressable no valid value 0 to 59 decimal min minutes time register function this register is incremented in 1-minute intervals once tcen in timecon is active. the min counts from 0 to 59 before rolling over to increment the hour time register. sfr address a4h power-on default value 00h bit addressable no valid value 0 to 59 decimal hour hours time register function this register is incremented in 1-hour intervals once tcen in timecon is active. the hour sfr counts from 0 to 23 before rolling over to 0. sfr address a5h power-on default value 00h bit addressable no valid value 0 to 23 decimal
rev. 0 ADUC816 C46C wdcon watchdog timer control register sfr address c0h power-on default value 10h bit addressable yes 3 e r p2 e r p1 e r p0 e r pr i d ws d we d wr w d w table xvii. wdcon sfr bit designations bit name description 7 pre3 watchdog timer prescale bits. 6 pre2 the watchdog timeout period is given by the equation: t wd = (2 pre (2 9 /f pll )) 5 pre1 (0 pre 7; f pll = 32.768 khz) 4 pre0 pre3 pre2 pre1 pre0timout period (ms) action 0 0 0 0 15.6 reset or interrupt 0 0 0 1 31.2 reset or interrupt 0 0 1 0 62.5 reset or interrupt 0 0 1 1 125 reset or interrupt 0 1 0 0 250 reset or interrupt 0 1 0 1 500 reset or interrupt 0 1 1 0 1000 reset or interrupt 0 1 1 1 2000 reset or interrupt 1 0 0 0 0.0 immediate reset pre3? > 1001 reserved 3 wdir watchdog interrupt response enable bit. if this bit is set by the user, the watchdog will generate an interrupt response instead of a system reset when the watchdog timeout period has expired. this interrupt is not disabled by the clr ea instruction and it is also a fixed, high-priority interrupt. if the watchdog is not being used to monitor the system, it can alternatively be used as a timer. the prescaler is used to set the timeout period in which an interrupt will be generated. (see also note 1, table xxxiv in the interrupt system section.) 2 wds watchdog status bit. set by the watchdog controller to indicate that a watchdog timeout has occurred. cleared by writing a ??or by an external hardware reset. it is not cleared by a watchdog reset. 1 wde watchdog enable bit. set by user to enable the watchdog and clear its counters. if this bit is not set by the user within the watchdog timeout period, the watchdog will generate a reset or interrupt, depending on wdir. cleared under the following conditions, user writes 0, watchdog reset (w dir = 0); hardware reset; psm interrupt. 0 wdwr watchdog write enable bit. to write data into the wdcon sfr involves a double instruction sequence. the wdwr bit must be set and the very next instruction must be a write instruction to the wdcon sfr. e.g., clr ea ; disable interrupts while writing to wdt setb wdwr ; allow write to wdcon mov wdcon, #72h ; enable wdt for 2.0s timeout set b ea ; enable interrupts again (if rqd) watchdog timer the purpose of the watchdog timer is to generate a device reset or inte rrupt within a reasonable amount of time if the ADUC816 enters an erroneous state, possibly due to a programming error, electrical noise, or rfi. the watchdog function can be disabled by clearing the wde (watchdog enable) bit in the watchdog control (wdcon) sfr. when enabled; the watchdog circuit will generate a system reset or interrupt (wds) if the user program fails to set the watchdog (wde) bit within a predetermined amount of time (see pre3? bits in wdcon). the watchdog timer itself is a 16-bit counter that is clocked at 32.768 khz. the watchdog time-out interval can be adjusted via the pre3? bits in wd con. full control and status of the watchdog timer function can be controlled via the watchdog timer control sfr (wdcon). the wdcon sfr can only be written by user software if the double write sequence described in wdwr below is initiated on every write access to the wdcon sfr.
rev. 0 ADUC816 C47C power supply monitor as its name suggests, the power supply monitor, once enabled, monitors both supplies (avdd or dvdd) on the ADUC816. it will indicate when any of the supply pins drop below one of four user-selectable voltage trip points from 2.63 v to 4.63 v. for correct operation of the power supply monitor function, av dd must be equal to or greater than 2.7 v. monitor function is controlled via the psmcon sfr. if enabled via the ieip2 sfr, the monitor will interrupt the core using the psmi bit in the psmcon sfr. this bit will not be cleared until the failing power supply has returned a bove the trip point for at least 250 ms. this monitor function allows the user to save working registers to avoid pos sible data loss due to the low supply condi- tion, and also ensures that normal code execution will not resume until a safe supply level has been well established. the supply monitor is also protected against spurious glitches trig- gering the interrupt circuit. psmcon power supply monitor control register sfr address dfh power-on default value deh bit addressable no d p m ca p m ci m s p1 d p t0 d p t1 a p t0 a p tn e m s p table xviii. psmcon sfr bit designations bit name description 7 cmpd dvdd comparator bit. this is a read-only bit and directly reflects the state of the dvdd comparator. read ??indicates the dvdd supply is above its selected trip point. read ??indicates the dvdd supply is below its selected trip point. 6 cmpa avdd comparator bit. this is a read-only bit and directly reflects the state of the avdd comparator. read ??indicates the avdd supply is above its selected trip point. read ??indicates the avdd supply is below its selected trip point. 5 psmi power supply monitor interrupt bit. this bit will be set high by the microconverter if either cmpa or cmpd are low, indicating low analog or digital supply. the psmi bit can be used to interrupt the processor. once cmpd and/or cmpa return (and remain) high, a 250 ms counter is started. when this counter times out, the psmi interrupt is cleared. psmi can also be written by the user. however, if either com- parator output is low, it is not possible for the user to clear psmi. 4 tpd1 dvdd trip point selection bits. 3 tpd0 these bits select the dvdd trip-point voltage as follows: tpd1 tpd0 selected dvdd trip point (v) 004.63 013.08 102.93 112.63 2 tpa1 avdd trip point selection bits. 1 tpa0 these bits select the avdd trip-point voltage as follows: tpa1 tpa0 selected avdd trip point (v) 004.63 013.08 102.93 112.63 0 psmen power supply monitor enable bit. set to ??by the user to enable the power supply monitor circuit. cleared to ??by the user to disable the power supply monitor circuit.
rev. 0 ADUC816 C48C serial peripheral interface the ADUC816 integrates a complete hardware serial peripheral interface (spi) interface on-chip. spi is an industry standard syn- chronous serial interface that allows eight bits of data to be synchronously transmitted and received simultaneously, i.e., full duplex. it should be noted that the spi physical interface is shared with the i 2 c interface and therefore the user can only enable one or the other interface at any given time (see spe in spicon below). the system can be configured for master or slave op era- tion and typically consists of four pins, namely: miso (master in, slave out data i/o pin), pin 14 the miso (master in slave out) pin is configured as an input line in master mode and an output line in slave mode. the miso line on the master (data in) should be connected to the miso line in the slave device (data out). the data is transferred as byte wide (8-bit) serial data, msb first. mosi (master out, slave in pin), pin 27 the mosi (master out slave in) pin is configured as an output line in master mode and an input line in slave mode. the mosi line on the master (data out) should be connected to the mosi line in the slave device (data in). the data is transferred as byte wide (8-bit) serial data, msb first. sclock (serial clock i/o pin), pin 26 the master clock (sclock) is used to synchronize the data being transmitted and received through the mosi and miso data lines. a single data bit is transmitted and received in each sclock period. therefore, a byte is transmitted/received after eight sclock periods. the sclock pin is configured as an output in master mode and as an input in slave mode. in master mode the bit-rate, polarity and phase of the clock are controlled by the cpol, cpha, spr0 and spr1 bits in the spicon sfr (see table xix below). in slave mode the spicon register will have to be configured with the phase and polarity (cpha and cpol) of the expected input clock. in both master and slave mode the data is transmitted on one edge of the sclock signal and sampled on the other. it is important therefore that the cpha and cpol are configured the same for the master and slave devices. ss (slave select input pin), pin 13 the slave select ( ss ) input pin is only used when the ADUC816 is configured in slave mode to enable the spi peripheral. this line is active low. data is only received or transmitted in slave mode when the ss pin is low, allowing the ADUC816 to be used in single master, multislave spi configurations. if cpha = 1 then the ss input may be permanently pulled low. with cpha = 0 then the ss input must be driven low before the first bit in a byte wide transmission or reception and return high again after the last bit in that byte wide transmission or reception. in spi slave mode, the logic level on the external ss pin (pin 13), can be read via the spr0 bit in the spicon sfr. the following sfr registers are used to control the spi inter face. spicon: spi control register sfr address f8h power-on default value 04h bit addressable yes i p s il o c we p sm i p sl o p ca h p c1 r p s0 r p s table xix. spicon sfr bit designations bit name description 7 ispi spi interrupt bit. set by microconverter at the end of each spi transfer. cleared directly by user code or indirectly by reading the spidat sfr 6 wcol write collision error bit. set by microconverter if spidat is written to while an spi transfer is in progress. cleared by user code. 5 spe spi interface enable bit. set by user to enable the spi interface. cleared by user to enable the i 2 c interface. 4 spim spi master/slave mode select bit. set by user to enable master mode operation (sclock is an output). cleared by user to enable slave mode operation (sclock is an input). 3 cpol clock polarity select bit. set by user if sclock idles high. cleared by user if sclock idles low. 2 cpha clock phase select bit. set by user if leading sclock edge is to transmit data. cleared by user if trailing sclock edge is to transmit data.
rev. 0 ADUC816 C49C table xix. spicon sfr bit designations ( continued ) bit name description 1 spr1 spi bit-rate select bits. 0 spr0 these bits select the sclock rate (bit-rate) in master mode as follows: spr1 spr0 selected bit rate 00f core /2 01f core /4 10f core /8 11f core /16 in spi slave mode, i.e., spim = 0, the logic level on the external ss pin (pin 13), can be read via the spr0 bit. note the cpol and cpha bits should both contain the same values for master and slave devices. spidat spi data register function the spidat sfr is written by the user to transmit data over the spi interface or read by user code to read data just received by the spi interface. sfr address f7h power-on default value 00h bit addressable no using the spi interface depending on the configuration of the bits in the spicon sfr shown in table xix, the ADUC816 spi interface will transmit or receive data in a number of possible modes. figure 32 shows all possible ADUC816 spi configurations and the timing rela- tionships and synchronization between the signals involved. also shown in this figure is the spi interrupt bit (ispi) and how it is triggered at the end of each byte-wide communica tion. sclock (cpol = 1) sclock (cpol = 0) (cpha = 1) (cpha = 0) sample input ispi flag data output ispi flag sample input data output ? ? msb bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 lsb ss msb bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 lsb figure 32. spi timing, all modes spi interface?aster mode in master mode, the sclock pin is always an output and gener- ates a burst of eight clocks whenever user code writes to the spidat register. the s clock bit rate is determined by spr0 and spr1 in spicon. it should also be noted that the ss pin is not used in master mode. if the ADUC816 needs to assert the ss pin on an external slave device, a port digital output pin should be used. in master mode a byte transmission or reception is initiated by a write to spidat. eight clock periods are generated via the sclock pin and the spidat byte being transmitted via mosi. with each sclock period a data bit is also sampled via miso. after eight clocks, the transmitted byte will have been completely transmitted and the input byte will be waiting in the input shift register. the ispi flag will be set automatically and an interrupt will occur if enabled. the value in the shift register will be latched into spidat. spi interface?lave mode in slave mode the sclock is an input. the ss pin must also be driven low externally during the byte communication. transmission is also initiated by a write to spidat. in slave mode, a data bit is transmitted via miso and a data bit is re ceived via mosi through each input sclock period. after eight clocks, the transmitted byte will have been completely transmitted and the input byte will be waiting in the input shift register. the ispi flag will be set automatically and an interrupt will occur if enabled. the value in the shift register will be latched into spidat only when the transmission/reception of a byte has been completed. the end of transmission occurs after the eighth clock has been received, if cpha = 1 or when ss returns high if cpha = 0.
rev. 0 ADUC816 C50C i 2 c-compatible interface the ADUC816 supports a 2-wire serial interface mode which is i 2 c compatible. the i 2 c-compatible interface shares its pins with the on-chip spi interface and therefore the user can only enable one or the other interface at any given time (see spe in i2cadd i 2 c address register function holds the i 2 c peripheral address for the part. it may be overwritten by user code. technical note uc001 at www.analog.com/microconverter describes the format of the i 2 c stan- dard 7-bit address in detail. sfr address 9bh power-on default value 55h bit addressable no i2cdat i 2 c data register function the i2cdat sfr is written by the user to transmit data over the i 2 c interface or read by user code to read data just received by the i 2 c interface accessing i2cdat automatically clears any pending i 2 c inter rupt and the i2ci bit in the i2c con sfr. user software should only access i2cdat once per interrupt cycle. sfr address 9ah power-on default value 00h bit addressable no spicon previ ously). an application note describing the operation of this interface as implemented is available from the microconverter website at www.analog.com/microconverter. this interface can be configured as a software master or hard- ware slave, and uses two pins in the interface. sdata (pin 27) serial data i/o pin sclock (pin 26) serial clock three sfrs are used to control the i 2 c-compatible interface. these are described below: i2ccon: i 2 c control register sfr address e8h power-on default value 00h bit addressable yes o d me d mo c mi d mm c 2 is r c 2 ix t c 2 ii c 2 i table xx. i2ccon sfr bit designations bit name description 7 mdo i 2 c software master data output bit (master mode only). this data bit is used to implement a master i 2 c transmitter interface in software. data written to this bit will be output on the sdata pin if the data output enable (mde) bit is set. 6 mde i 2 c software master data output enable bit (master mode only). set by user to enable the sdata pin as an output (tx). cleared by the user to enable sdata pin as an input (rx). 5 mco i 2 c software master clock output bit (master mode only). this data bit is used to implement a master i 2 c transmitter interface in software. data written to this bit will be outputted on the sclock pin. 4 mdi i 2 c software master data input bit (master mode only). this data bit is used to implement a master i 2 c receiver interface in software. data on the s data pin is latched into this bit on sclock if the data output enable (mde) bit is ?. 3 i2cm i 2 c master/slave mode bit. set by user to enable i 2 c software master mode. cleared by user to enable i 2 c hardware slave mode. 2 i2crs i 2 c reset bit (slave mode only). set by user to reset the i 2 c interface. cleared by user code for normal i 2 c operation. 1 i2ctx i 2 c direction transfer bit (slave mode only). set by the microconverter if the interface is transmitting. cleared by the microconverter if the interface is receiving. 0 i2ci i 2 c interrupt bit (slave mode only). set by the microconverter after a byte has been transmitted or received. cleared automatically when user code reads the i2cdat sfr (see i2cdat below).
rev. 0 ADUC816 C51C 8051-compatible on-chip peripherals this section gives a brief overview of the various secondary periph- eral circuits are also available to the user on-chip. these rem aining functions are fully 8051-compatible and are controlled via stan dard 8051 sfr bit definitions. parallel i/o ports 0? the ADUC816 uses four input/output ports to exchange data with external devices. in addition to performing general-purpose i/o, some ports are capable of external memory operations; others are multiplexed with an alternate function for the peripheral features on the device. in general, when a peripheral is enabled, that pin may not be used as a general purpose i/o pin. port 0 is an 8-bit open drain bidirectional i/o port that is directly controlled via the port 0 sfr (sfr address = 80 hex). port 0 pins that have 1s written to them via the port 0 sfr will be configured as open drain and will therefore float. in that state, port 0 pins can be used as high impedance inputs. an external pull-up resistor will be required on port 0 outputs to force a valid logic high level externally. port 0 is also the multiplexed low-order address and data bus during accesses to external pro- gram or data memory. in this application it uses strong internal pull-ups when emitting 1s. port 1 is also an 8-bit port directly controlled via the p1 sfr (sfr address = 90 hex). the port 1 pins are divided into two distinct pin groupings. p1.0 and p1.1 pins on port 1 are bidirectional digital i/o pins with internal pull-ups. if p1.0 and p1.1 have 1s written to them via the p1 sfr, these pins are pulled high by the internal pull-up resis- tors. in this state they can also be used as inputs; as input pins being externally pulled low, they will source current because of the internal pull-ups. with 0s written to them, both these pins will drive a logic low output voltage (vol) and will be capable of sinking 10 ma compared to the standard 1.6 ma sink capa- bility on the other port pins. these pins also have various secondary functions described in table xxi. table xxi. port 1, alternate pin functions pin alternate function p1.0 t2 (timer/counter 2 external input) p1.1 t2ex (timer/counter 2 capture/reload trigger) the remaining port 1 pins (p1.2?1.7) can only be configured as analog input (adc), analog output (dac) or digital input pins. by (power-on) default these pins are configured as analog inputs, i.e., 1 written in the corresponding port 1 register bit. to configure any of these pins as digital inputs, the user should write a ??to these port bits to configure the corresponding pin as a high impedance digital input. port 2 is a bidirectional port with internal pull-up resistors di rectly controlled via the p2 sfr (sfr address = a0 hex). port 2 pins that have 1s written to them are pulled high by the internal pull-up resistors and, in that state, they can be used as inputs. as inputs, port 2 pins being pulled externally low will source current because of the internal pull-up resistors. port 2 emits the high order address bytes during fetches from external program memory and middle and high order address bytes during accesses to the 16-bit external data memory space. port 3 is a bidirectional port with internal pull-ups directly controlled via the p2 sfr (sfr address = b0 hex). port 3 pins that have 1s written to them are pulled high by the internal pull- ups and in that state they can be used as inputs. as inputs, port 3 pins being pulled externally low will source current because of the internal pull-ups. port 3 pins also have various secondary functions described in table xxii. table xxii. port 3, alternate pin functions pin alternate function p3.0 rxd (uart input pin) (or serial data i/o in mode 0) p3.1 txd (uart output pin) (or serial clock output in mode 0) p3.2 int0 (external interrupt 0) p3.3 int1 (external interrupt 1) p3.4 t0 (timer/counter 0 external input) p3.5 t1 (timer/counter 1 external input) p3.6 wr (external data memory write strobe) p3.7 rd (external data memory read strobe) the alternate functions of p1.0, p1.1, and port 3 pins can only be activated if the corresponding bit latch in the p1 and p3 sfrs contains a 1. otherwise, the port pin is stuck at 0. timers/counters the ADUC816 has three 16-bit timer/counters: timer 0, timer 1, and timer 2. the timer/counter hardware has been included on-chip to relieve the processor core of the overhead inherent in implementing timer/counter functionality in soft- ware. each timer/counter consists of two 8-bit registers thx and tlx (x = 0, 1 and 2). all three can be configured to operate either as timers or event counters. in ?imer?function, the tlx register is incremented every machine cycle. thus one can think of it as counting machine cycles. since a machine cycle consists of 12 core clock periods, the maximum count rate is 1/12 of the core clock frequency. in counter?function, the tlx register is incremented by a 1-to-0 transition at its corresponding external input pin, t0, t1, or t2. in this function, the external input is sampled during s5p2 of every machine cycle. when the samples show a high in one cycle and a low in the next cycle, the count is incremented. the new count value appears in the register during s3p1 of the cycle following the one in which the transition was detected. since it takes two machine cycles (16 core clock periods) to recognize a 1-to-0 transition, the maximum count rate is 1/16 of the core clock frequency. th ere are no restrictions on the duty cycle of the external input signal, but to ensure that a given level is sampled at least once before it changes, it must be held for a mini- mum of one full ma chine cycle. remember that the core clock frequency is programmed via the cd0? selection bits in the pllcon sfr.
rev. 0 ADUC816 C52C user configuration and control of all timer operating modes is achieved via three sfrs namely: tmod, tcon: control and configuration for timers 0 and 1. t2con: control and configuration for timer 2. tmod timer/counter 0 and 1 mode register sfr address 89h power-on default value 00h bit addressable no e t a g/ c t 1 m0 me t a g/ c t 1 m0 m table xxiii. tmod sfr bit designations bit name description 7 gate timer 1 gating control. set by software to enable timer/counter 1 only while int1 pin is high and tr1 control bit is set. cleared by software to enable timer 1 whenever tr1 control bit is set. 6c/ t timer 1 timer or counter select bit. set by software to select counter operation (input from t1 pin). cleared by software to select timer operation (input from internal system clock). 5 m1 timer 1 mode select bit 1 (used with m0 bit). 4 m0 timer 1 mode select bit 0. m1 m0 0 0 th1 operates as an 8-bit timer/counter. tl1 serves as 5-bit pre scaler. 0 1 16-bit timer/ counter. th1 and tl1 are cas caded; there is no prescaler. 1 0 8-bit auto-r eload timer/counter. th1 holds a value which is to be reloaded into tl1 each time it overflows. 1 1 timer/counter 1 stopped. 3 gate timer 0 gating control. set by software to enable timer/counter 0 only while int0 pin is high and tr0 control bit is set. cleared by software to enable timer 0 whenever tr0 control bit is set. 2c/ t timer 0 timer or counter select bit. set by software to select counter operation (input from t0 pin). cleared by software to select timer operation (input from internal system clock). 1 m1 timer 0 mode select bit 1. 0 m0 timer 0 mode select bit 0. m1 m0 0 0 th0 operates as an 8-bit timer/counter. tl0 serves as 5-bit prescaler. 0 1 16-bit timer/counter. th0 and tl0 are cascaded; there is no prescaler 1 0 8-bit auto-reload timer/counter. th0 holds a value which is to be reloaded into tl0 each time it overflows. 1 1 tl0 is an 8-bit timer/counter controlled by the standard timer 0 control bits. th0 is an 8-bit timer only, controlled by timer 1 control bits.
rev. 0 ADUC816 C53C tcon: timer/counter 0 and 1 control register sfr address 88h power-on default value 00h bit addressable yes 1 f t1 r t0 f t0 r t1 e i 1 1 t i 1 0 e i 1 0 t i 1 note 1 these bits are not used in the control of timer/counter 0 and 1, but are used instead in the control and monitoring of the exte rnal int0 and int1 interrupt pins. table xxiv. tcon sfr bit designations bit name description 7 tf1 timer 1 overflow flag. set by hardware on a timer/counter 1 overflow. cleared by hardware when the program counter (pc) vectors to the interrupt service routine. 6 tr1 timer 1 run control bit. set by user to turn on timer/counter 1. cleared by user to turn off timer/counter 1. 5 tf0 timer 0 overflow flag. set by hardware on a timer/counter 0 overflow. cleared by hardware when the pc vectors to the interrupt service routine. 4 tr0 timer 0 run control bit. set by user to turn on timer/counter 0. cleared by user to turn off timer/counter 0. 3 ie1 external interrupt 1 ( int1 ) flag. set by hardware by a falling edge or zero level being applied to external interrupt pin int1 , depend- ing on bit it1 state. cleared by hardware when the when the pc vectors to the interrupt service routine only if the inter- rupt was transition-activated. if level-activated, the external requesting source controls the request flag, rather than the on-chip hardware. 2 it1 external interrupt 1 (ie1) trigger type. set by software to specify edge-sensitive detection (i.e., 1-to-0 transition). cleared by software to specify level-sensitive detection (i.e., zero level). 1 ie0 external interrupt 0 ( int0 ) flag. set by hardware by a falling edge or zero level being applied to external interrupt pin int0 , depend- ing on bit it0 state. cleared by hardware when the pc vectors to the interrupt service routine only if the interrupt was transition-activated. if level-activated, the external requesting source controls the request flag, rather than the on-chip hardware. 0 it0 external interrupt 0 (ie0) trigger type. set by software to specify edge-sensitive detection (i.e., 1-to-0 transition). cleared by software to specify level-sensitive detection (i.e., zero level). timer/counter 0 and 1 data registers each timer consists of two 8-bit registers. these can be used as independent registers or combined to be a single 16-bit regist er depending on the timer mode configuration. th0 and tl0 timer 0 high byte and low byte. sfr address = 8chex, 8ahex respectively. th1 and tl1 timer 1 high byte and low byte. sfr address = 8dhex, 8bhex respectively.
rev. 0 ADUC816 C54C timer/counter 0 and 1 operating modes the following paragraphs describe the operating modes for timer/ counters 0 and 1. unless otherwise noted, it should be assumed that these modes of operation are the same for timer 0 as for timer 1. mode 0 (13-bit timer/counter) mode 0 configures an 8-bit timer/counter with a divide-by-32 prescaler. figure 33 shows mode 0 operation. 12 core clk * tf0 interrupt control p3.4/t0 gate p3.2/ int0 tr0 tl0 (5 bits) th0 (8 bits) c/ t = 0 c/ t = 1 * the core clock is the output of the pll as described on page 42. figure 33. timer/counter 0, mode 0 in this mode, the timer register is configured as a 13-bit register. as the count rolls over from all 1s to all 0s, it sets the timer overflow flag tf0. the overflow flag, tf0, can then be used to request an interrupt. the counted input is enabled to the timer when tr0 = 1 and either gate = 0 or int0 = 1. setting gate = 1 allows the timer to be controlled by external input int0 , to facilitate pulsewidth measurements. tr0 is a control bit in the special function regis- ter tcon; gate is in tmod. the 13-bit register consists of all eight bits of th0 and the lower five bits of tl0. the upper three bits of tl0 are indeterminate and should be ignored. setting the run flag (tr0) does not clear the registers. mode 1 (16-bit timer/counter) mode 1 is the same as mode 0, except that the timer register is running with all 16 bits. mode 1 is shown in figure 34. 12 core clk * tf0 interrupt control p3.4/t0 tl0 (8 bits) th0 (8 bits) c/ t = 0 c/ t = 1 gate p3.2/ int0 tr0 * the core clock is the output of the pll as described on page 42. figure 34. timer/counter 0, mode 1 mode 2 (8-bit timer/counter with autoreload) mode 2 configures the timer register as an 8-bit counter (tl0) with automatic reload, as shown in figure 35. overflow from tl0 not only sets tf0, but also reloads tl0 with the contents of th0, which is preset by software. the reload leaves th0 unchanged. 12 core clk * control p3.4/t0 tf0 tl0 (8 bits) interrupt c/ t = 0 c/ t = 1 reload th0 (8 bits) gate p3.2/ int0 tr0 * the core clock is the output of the pll as described on page 42. figure 35. timer/counter 0, mode 2 mode 3 (two 8-bit timer/counters) mode 3 has different effects on timer 0 and timer 1. timer 1 in mode 3 simply holds its count. the effect is the same as setting tr1 = 0. timer 0 in mode 3 establishes tl0 and th0 as two separate counters. this configuration is shown in figure 36. tl0 uses the timer 0 control bits: c/t, gate, tr0, int0 , and tf0. th0 is locked into a timer function (counting machine cycles) and takes over the use of tr1 and tf1 from timer 1. thus, th0 now controls the ?imer 1?interrupt. mode 3 is provided for applications requiring an extra 8-bit timer or counter. when timer 0 is in mode 3, timer 1 can be turned on and off by switching it out of, and into, its own mode 3, or can still be used by the serial interface as a baud rate generator . in fact, it can be used, in any application not requiring an interrupt from timer 1 itself. 12 core clk * tl0 (8 bits) tf0 interrupt control p3.4/t0 c/ t = 0 c/ t = 1 th0 (8 bits) tf1 interrupt core clk/12 tr1 core clk/12 control gate p3.2/ int0 tr0 * the core clock is the output of the pll as described on page 42. figure 36. timer/counter 0, mode 3
rev. 0 ADUC816 C55C t2con timer/counter 2 control register sfr address c8h power-on default value 00h bit addressable yes 2 f t2 f x ek l c rk l c t2 n e x e2 r t2 t n c2 p a c table xxv. t2con sfr bit designations bit name description 7 tf2 timer 2 overflow flag. set by hardware on a timer 2 overflow. tf2 will not be set when either rclk or tclk = 1. cleared by user software. 6 exf2 timer 2 external flag. set by hardware when either a capture or reload is caused by a negative transition on t2ex and exen2 = 1. cleared by user user software. 5 rclk receive clock enable bit. set by user to enable the serial port to use timer 2 overflow pulses for its receive clock in serial port modes 1 and 3. cleared by user to enable timer 1 overflow to be used for the receive clock. 4 tclk transmit clock enable bit. set by user to enable the serial port to use timer 2 overflow pulses for its transmit clock in serial port modes 1 and 3. cleared by user to enable timer 1 overflow to be used for the transmit clock. 3 exen2 timer 2 external enable flag. set by user to enable a capture or reload to occur as a result of a negative transition on t2ex if timer 2 is not being used to clock the serial port. cleared by user for timer 2 to ignore events at t2ex. 2 tr2 timer 2 start/stop control bit. set by user to start timer 2. cleared by user to stop timer 2. 1 cnt2 timer 2 timer or counter function select bit. set by user to select counter function (input from external t2 pin). cleared by user to select timer function (input from on-chip core clock). 0 cap2 timer 2 capture/reload select bit. set by user to enable captures on negative transitions at t2ex if exen2 = 1. cleared by user to enable auto-reloads with timer 2 overflows or negative transitions at t2ex when exen2 = 1. when either rclk = 1 or tclk = 1, this bit is ignored and the timer is forced to autoreload on timer 2 overflow. timer/counter 2 data registers timer/counter 2 also has two pairs of 8-bit data registers associated with it. these are used as both timer data registers and timer capture/reload registers. th2 and tl2 timer 2, data high byte and low byte. sfr address = cdhex, cchex respectively. rcap2h and rcap2l timer 2, capture/reload byte and low byte. sfr address = cbhex, cahex respectively.
rev. 0 ADUC816 C56C timer/counter 2 operating modes the following paragraphs describe the operating modes for timer/ counter 2. the operating modes are selected by bits in the t2con sfr as shown in table xxvi. table xxvi. timecon sfr bit designations rclk (or) tclk cap2 tr2 mode 0 0 1 16-bit autoreload 0 1 1 16-bit capture 1 x 1 baud rate x x 0 off 16-bit autoreload mode in ?utoreload?mode, there are two options, w hich are selected by bit exen2 in t2con. if exen2 = 0, then when timer 2 rolls over it not only sets tf2 but also causes the timer 2 regis ters to be reloaded with the 16-bit value in registers rcap2l and rcap2h, which are preset by software. if exen2 = 1, then timer 2 still performs the above, but with the added feature that a 1-to-0 transition at external input t2ex will also trigger the 16-bit reload and set exf2. the autoreload mode is illustrated in figure 37 below. core clk * 12 t2 pin c/ t2 = 0 c/ t2 = 1 tr2 control tl2 (8 bits) th2 (8 bits) reload tf2 exf2 timer interrupt exen2 control transition detector t2ex pin rcap2l rcap2h * the core clock is the output of the pll as described on page 42. figure 37. timer/counter 2, 16-bit autoreload mode tf2 core clk * 12 t2 pin tr2 control tl2 (8 bits) th2 (8 bits) capture exf2 timer interrupt exen2 control transition detector t2ex pin rcap2l rcap2h c/ t2 = 0 c/ t2 = 1 * the core clock is the output of the pll as described on page 42. figure 38. timer/counter 2, 16-bit capture mode 16-bit capture mode in the capture mode, there are again two options, which are selected by bit exen2 in t2con. if exen2 = 0, then timer 2 is a 16-bit timer or counter which, upon overflowing, sets bit tf2, the timer 2 overflow bit, which can be used to generate an inter- rupt. if exen2 = 1, then timer 2 still performs the above, but a l-to-0 transition on external input t2ex causes the current value in the timer 2 registers, tl2 and th2, to be captured into regis- ters rcap2l and rcap2h, respectively. in addition, the transition at t2ex causes bit exf2 in t2con to be set, and exf2, like tf2, can generate an interrupt. the capture mode is illustrated in figure 38. the baud rate generator mode is selected by rclk = 1 and/or tclk = 1. in either case if timer 2 is being used to generate the baud rate, the tf2 interrupt flag will not occur. hence timer 2 interrupts will not occur so they do not have to be disabled. in this mode the exf2 flag, however, can still cause interrupts and this can be used as a third external interrupt. baud rate generation will be described as part of the uart serial port operation in the following pages.
rev. 0 ADUC816 C57C uart serial interface the serial port is full duplex, meaning it can transmit and receive simultaneously. it is also receive-buffered, meaning it can commence reception of a second byte before a previously received byte has been read from the receive register. however, if the first byte still has not been read by the time reception of the second byte is complete, the first byte will be lost. the physical interface to the serial data network is via pins rxd(p3.0) and txd(p3.1) while the sfr interface to the uart is comprised of the fol- lowing registers. sbuf the serial port receive and transmit registers are both accessed through the sbuf sfr (sfr address = 99 hex). writing to sbuf loads the transmit register and reading sbuf accesses a physically separate receive register. scon uart serial port control register sfr address 98h power-on default value 00h bit addressable yes 0 m s1 m s2 m sn e r8 b t8 b ri ti r table xxvii. scon sfr bit designations bit name description 7 sm0 uart serial mode select bits. 6 sm1 these bits select the serial port operating mode as follows: sm0 sm1 selected operating mode 0 0 mode 0: shift register, fixed baud rate (core_clk/2) 0 1 mode 1: 8-bit uart, variable baud rate 1 0 mode 2: 9-bit uart, fixed baud rate (core_clk/64) or (core_clk/32) 1 1 mode 3: 9-bit uart, variable baud rate 5 sm2 multiprocessor communication enable bit. enables multiprocessor communication in modes 2 and 3. in mode 0, sm2 should be cleared. in mode 1, if sm2 is set, ri will not be activated if a valid stop bit was not received. if sm2 is cleared, ri will be set as soon as the byte of data has been received. in modes 2 or 3, if sm2 is set, ri will not be activated if the received ninth data bit in rb8 is 0. if sm2 is cleared, ri will be set as soon as the byte of data has been received. 4 ren serial port receive enable bit. set by user software to enable serial port reception. cleared by user software to disable serial port reception. 3 tb8 serial port transmit (bit 9). the data loaded into tb8 will be the ninth data bit that will be transmitted in modes 2 and 3. 2 rb8 serial port receiver bit 9. the ninth data bit received in modes 2 and 3 is latched into rb8. for mode 1 the stop bit is latched into rb8. 1 ti serial port transmit interrupt flag. set by hardware at the end of the eighth bit in mode 0, or at the beginning of the stop bit in modes 1, 2, and 3. ti must be cleared by user software. 0 ri serial port receive interrupt flag. set by hardware at the end of the eighth bit in mode 0, or halfway through the stop bit in modes 1, 2, and 3. ri must be cleared by software.
rev. 0 ADUC816 C58C mode 0: 8-bit shift register mode mode 0 is selected by clearing both the sm0 and sm1 bits in the sfr scon. serial data enters and exits through rxd. txd outputs the shift clock. eight data bits are transmitted or received. transmission is initiated by any instruction that writes to sbuf. the data is shifted out of the rxd line. the eight bits are trans- mitted with the least-significant bit (lsb) first, as shown in figure 39. core clk ale rxd (data out) txd (shift clock) data bit 0 data bit 1 data bit 6 data bit 7 s6 s5 s4 s3 s2 s1 s6 s5 s4 s4 s3 s2 s1 s6 s5 s4 s3 s2 s1 machine cycle 8 machine cycle 7 machine cycle 2 machine cycle 1 figure 39. uart serial port transmission, mode 0 reception is initiated when the receive enable bit (ren) is 1 and the receive interrupt bit (ri) is 0. when ri is cleared the data is clocked into the rxd line and the clock pulses are output from the txd line. mode 1: 8-bit uart, variable baud rate mode 1 is selected by clearing sm0 and setting sm1. each data byte (lsb first) is preceded by a start bit(0) and followed by a stop bit(1). therefore 10 bits are transmitted on txd or received on rxd. the baud rate is set by the timer 1 or timer 2 overflow rate, or a combination of the two (one for transmission and the other for reception). transmission is initiated by writing to sbuf. the ?rite to sbuf?s ignal also loads a 1 (stop bit) into the ninth bit position of the transmit shift register. the data is output bit by bit until the stop bit ap pears on txd and the transmit inter rupt flag (ti) is automatically set as shown in figure 40. txd ti (scon.1) start bit d0 d1 d2 d3 d4 d5 d6 d7 stop bit set interrupt i.e. , ready for more data figure 40. uart serial port transmission, mode 0 reception is initiated when a 1-to-0 transition is detected on rxd. assuming a valid start bit was detected, character reception continues. the start bit is skipped and the eight data bits are clocked into the serial port shift register. when all eight bits have been clocked in, the following events occur: the eight bits in the receive shift register are latched into sbuf the ninth bit (stop bit) is clocked into rb8 in scon the receiver interrupt flag (ri) is set if, and only if, the following conditions are met at the time the final shift pulse is generated: ri = 0, and either sm2 = 0, or sm2 = 1 and the received stop bit = 1. if either of these conditions is not met, the received frame is irretrievably lost, and ri is not set. mode 2: 9-bit uart with fixed baud rate mode 2 is selected by setting sm0 and clearing sm1. in this mode the uart operates in 9-bit mode with a fixed baud rate. the baud rate is fixed at core_clk/64 by default, although by setting the smod bit in pcon, the frequency can be doubled to core_clk/32. eleven bits are transmitted or received, a start bit(0), eight data bits, a programmable ninth bit and a stop bit(1). the ninth bit is most often used as a parity bit, although it can be used for anything, including a ninth data bit if required. to transmit, the eight data bits must be written into sbuf. the ninth bit must be written to tb8 in scon. when transmission is initiated the eight data bits (from sbuf) are loaded onto the transmit shift register (lsb first). the contents of tb8 are loaded into the ninth bit position of the transmit shift register. the trans- mission will start at the next valid baud rate clock. the ti flag is set as soon as the stop bit appears on txd. reception for mode 2 is similar to that of mode 1. the eight data bytes are input at rxd (lsb first) and loaded onto the receive shift register. when all eight bits have been clocked in, the following events occur: the eight bits in the receive shift register are latched into sbuf the ninth data bit is latched into rb8 in scon the receiver interrupt flag (ri) is set if, and only if, the following conditions are met at the time the final shift pulse is generated: ri = 0, and either sm2 = 0, or sm2 = 1 and the received stop bit = 1. if either of these conditions is not met, the received frame is irretrievably lost, and ri is not set. mode 3: 9-bit uart with variable baud rate mode 3 is selected by setting both sm0 and sm1. in this mode the 8051 uart serial port operates in 9-bit mode with a variable baud rate determined by either timer 1 or timer 2. the opera- tion of the 9-bit uart is the same as for mode 2 but the baud rate can be varied as for mode 1. in all four modes, transmission is initiated by any instruction that uses sbuf as a destination register. reception is initiated in mode 0 by the condition ri = 0 and ren = 1. reception is initiated in the other modes by the incoming start bit if ren = 1. uart serial port baud rate generation mode 0 baud rate generation the baud rate in mode 0 is fixed: mode 0 baud rate = (core clock frequency 1 /12) note 1 in these descriptions core clock frequency refers to the core clock frequency selected via the cd0? bits in the pllcon sfr. mode 2 baud rate generation the baud rate in mode 2 depends on the value of the smod bit in the pcon sfr. if smod = 0, the baud rate is 1/64 of the core clock. if smod = 1, the baud rate is 1/32 of the core clock: mode 2 baud rate = (2 smod /64) (core clock frequency) modes 1 and 3 baud rate generation the baud rates in modes 1 and 3 are determined by the overflow rate in timer 1 or timer 2, or both (one for transmit and the other for receive).
rev. 0 ADUC816 C59C timer 1 generated baud rates when timer 1 is used as the baud rate generator, the baud rates in modes 1 and 3 are determined by the timer 1 overflow rate and the value of smod as follows: modes 1 and 3 baud rate = (2 smod /32) (timer 1 overflow rate) the timer 1 interrupt should be disabled in this application. the timer itself can be configured for either timer or counter opera- tion, and in any of its three running modes. in the most typical application, it is configured for timer operation, in the autoreload mode (high nibble of tmod = 0100binary). in that case, the baud rate is given by the formula: modes 1 and 3 baud rate = (2 smod /32) (core clock/(12 [256-th1])) a very low baud rate can also be achieved with timer 1 by leaving the timer 1 interrupt enabled, and configuring the timer to run as a 16-bit timer (high nibble of tmod = 0100binary), and using the timer 1 interrupt to do a 16-bit software reload. table xxviii below, shows some commonly-used baud rates and how they might be calculated from a core clock frequency of 1. 5728 mhz and 12.58 mhz. generally speaking, a 5% error is tolerable using asynchronous (start/stop) communications. table xxviii. commonly-used baud rates, timer 1 ideal core smod th1-reload actual % baud clk value value baud error 9600 12.58 1 ? (f9h) 9362 2.5 2400 12.58 1 ?7 (e5h) 2427 1.1 1200 12.58 1 ?5 (c9h) 1192 0.7 1200 1.57 1 ? (f9h) 1170 2.5 timer 2 generated baud rates baud rates can also be generated using timer 2. using timer 2 is similar to using timer 1 in that the timer must overflow 16 times before a bit is transmitted/received. because timer 2 has a 16-bit autoreload mode a wider range of baud rates is possible using timer 2. modes 1 and 3 baud rate = (1/16) (timer 2 overflow rate) therefore, when timer 2 is used to generate baud rates, the timer increments every two clock cycles and not every core machine cycle as before. hence, it increments six times faster than timer 1, and therefore baud rates six times faster are possible. because timer 2 has 16-bit autoreload capability, very low baud rates are still possible. timer 2 is selected as the baud rate generator by setting the tclk and/or rclk in t2con. the baud rates for transmit and receive can be simultaneously different. setting rclk and/or tclk puts timer 2 into its baud rate generator mode as shown in figure 41. in this case, the baud rate is given by the formula: modes 1 and 3 baud rate = (core clk)/(32 [65536 ?(rcap2h, rcap2l)]) table xxix shows some commonly used baud rates and how they might be calculated from a core clock frequency of 1.5728 mhz and 12.5829 mhz. table xxix. commonly used baud rates, timer 2 ideal core rcap2h rcap2l actual % baud clk value value baud error 19200 12.58 ? (ffh) ?0 (ech) 19661 2.4 9600 12.58 ? (ffh) ?1 (d7h) 9591 0.1 2400 12.58 ? (ffh) ?64 (5ch) 2398 0.1 1200 12.58 ? (feh) ?2 (b8h) 1199 0.1 9600 1.57 ? (ffh) ? (fbh) 9830 2.4 2400 1.57 ? (ffh) ?0 (ech) 2457 2.4 1200 1.57 ? (ffh) ?1 (d7h) 1199 0.1 core clk * 2 t2 pin tr2 control tl2 (8 bits) th2 (8 bits) reload exen2 control t2ex pin rcap2l rcap2h note: osc. freq. is divided by 2, not 12. timer 2 overflow 2 16 16 rclk tclk rx clock tx clock 0 0 1 1 1 0 smod timer 1 overflow transition detector exf 2 timer 2 interrupt note availability of additional external interrupt c/ t2 = 0 c/ t2 = 1 * the core clock is the output of the pll as described on page 42. figure 41. timer 2, uart baud rates
rev. 0 ADUC816 C60C interrupt system the ADUC816 provides a total of twelve interrupt sources with two priority levels. the control and configuration of the interru pt system is carried out through three interrupt-related sfrs. ie: interrupt enable register. ip: interrupt priority register. ieip2: secondary interrupt priority-interrupt register. ie: interrupt enable register sfr address a8h power-on default value 00h bit addressable yes a ec d a e2 t es e1 t e1 x e0 t e0 x e table xxx. ie sfr bit designations bit name description 7 ea written by user to enable ??or disable ??all interrupt sources 6 eadc written by user to enable ??or disable ??adc interrupt 5 et2 written by user to enable ??or disable ??timer 2 interrupt 4 es written by user to enable ??or disable ??uart serial port interrupt 3 et1 written by user to enable ??or disable ??timer 1 interrupt 2 ex1 written by user to enable ??or disable ??external interrupt 1 1 et0 written by user to enable ??or disable ??timer 0 interrupt 0 ex0 written by user to enable ??or disable ??external interrupt 0 ip: interrupt priority register sfr address b8h power-on default value 00h bit addressable yes - - -c d a p2 t ps p1 t p1 x p0 t p0 x p table xxxi. ip sfr bit designations bit name description 7 --- reserved for future use. 6 padc written by user to select adc interrupt priority (??= high; ??= low) 5 pt2 written by user to select timer 2 interrupt priority (??= high; ??= low) 4 ps written by user to select uart serial port interrupt priority (??= high; ??= low) 3 pt1 written by user to select timer 1 interrupt priority (??= high; ??= low) 2 px1 written by user to select external interrupt 1 priority (??= high; ??= low) 1 pt0 written by user to select timer 0 interrupt priority (??= high; ??= low) 0 px0 written by user to select external interrupt 0 priority (??= high; ??= low)
rev. 0 ADUC816 C61C ieip2: secondary interrupt enable and priority register sfr address a9h power-on default value a0h bit addressable no - - -i t pm s p pi s p- - -i t em s p ei s e table xxxii. ieip2 sfr bit designations bit name description 7 --- reserved for future use. 6 pti written by user to select tic interrupt priority (??= high; ??= low). 5 ppsm written by user to select power supply monitor interrupt priority (??= high; ??= low). 4 psi written by user to select spi/i 2 c serial port interrupt priority (??= high; ??= low). 3 --- reserved, this bit must be ?. 2 eti written by user to enable ??or disable ??tic interrupt. 1 epsm written by user to enable ??or disable ??power supply monitor interrupt. 0 esi written by user to enable ??or disable ??spi/i 2 c serial port interrupt. interrupt priority the interrupt enable registers are written by the user to enable individual interrupt sources, while the interrupt priority registers allow the user to select one of two priority levels for each inter rupt. an interrupt of a high priority may interrupt the service routine of a low priority interrupt, and if two interrupts of different priority occur at the same time, the higher level interrupt will be serviced first. an interrupt cannot be interrupted by another interrupt of the same priority level. if two interrupts of the same priority level occur simultaneously, a polling sequence is observed as shown in table xxxiii. table xxxiii. priority within an interrupt level source priority description psmi 1 (highest) power supply monitor inter rupt wds 2 watchdog interrupt ie0 3 external interrupt 0 rdy0/rdy1 4 adc interrupt tf0 5 timer/counter 0 interrupt ie1 6 external interrupt 1 tf1 7 timer/counter 1 interrupt i2ci + ispi 8 i 2 c/spi interrupt ri + ti 9 serial interrupt tf2 + exf2 10 timer/counter 2 interrupt tii 11 (lowest) time interval counter inter rupt interrupt vectors when an interrupt occurs the program counter is pushed onto the stack and the corresponding interrupt vector address is loaded into the program counter. the interrupt vector addresses are shown in table xxxiv. table xxxiv. interrupt vector addresses source vector address ie0 0003 hex tf0 000b hex ie1 0013 hex tf1 001b hex ri + ti 0023 hex tf2 + exf2 002b hex rdy0/rdy1 (adc) 0033 hex ii 2 c + ispi 003b hex psmi 0043 hex tii 0053 hex wds (wdir = 1) * 005b hex * the watchdog can be configured to generate an interrupt instead of a reset when it times out. this is used for logging errors or to examine the internal status of the microcontroller core to understand, from a software debug point of view, why a watchdog timeout occurred. the watchdog interrupt is slightly different from the normal interrupts in that its priority level is always set to 1 and it is not possible to disable the interrupt via the global disable bit (ea) in the ie sfr. this is done to ensure that the interrupt will always be responded to if a watchdog timeout occurs. the watchdog will only produce an interrupt if the watch- dog timeout is greater than zero.
rev. 0 ADUC816 C62C ADUC816 hardware design considerations this section outlines some of the key hardware design consider- ations that must be addressed when integrating the ADUC816 into any hardware system. clock oscillator as described earlier, the core clock frequency for the ADUC816 is generated from an on-chip pll that locks onto a multiple (384 times) of 32.768 khz. the latter is generated from an inter- nal clock oscillator. to use the internal clock oscillator, connect a 32.768 khz parallel resonant crystal between xtal1 and xtal2 pins (32 and 33) as shown in figure 42. as shown in the typical external crystal connection diagram in figure 42, two internal 12 pf capacitors are provided on-chip. these are connected internally, directly to the xtal1 and xtal2 pins and the total input capacitances at both pins is detailed in the specification section of this data sheet. the value of the total load capacitance required for the external crystal should be the value recommended by the crystal manufacturer for use with that specific crystal. in many cases, because of the on-chip capacitors, additional external load capacitors will not be re quired. xtal2 xtal1 32.768khz to internal pll ADUC816 12pf 12pf figure 42. external parallel resonant crystal connections external memory interface in addition to its internal program and data memories, the ADUC816 can access up to 64 kbytes of external program memory (rom/prom/etc.) and up to 16 mbytes of external data memory (sram). to select from which code space (internal or external program memory) to begin executing instructions, tie the ea (external access) pin high or low, respectively. when ea is high (pulled up to v dd ), user program execution will start at address 0 of the internal 8 kbytes flash/ee code space. when ea is low (tied to ground) user program execution will start at address 0 of the external code space. in either case, addresses above 1fff hex (8k) are m apped to the external space. note that a second very important function of the ea pin is described in the single pin emulation mode section of this data sheet. external program memory (if used) must be connected to the ADUC816 as illustrated in figure 43. note that 16 i/o lines (ports 0 and 2) are dedicated to bus functions during external program memory fetches. port 0 (p0) serves as a multiplexed address/data bus. it emits the low byte of the program counter (pcl) as an address, and then goes into a float state awaiting the arrival of the code byte from the program memory. during the time that the low byte of the program counter is valid on p0, the signal ale (address latch enable) clocks this byte into an address l atch. meanwhile, port 2 (p2) emits the high byte of the program counter (pch), then psen strobes the eprom and the code byte is read into the ADUC816. latch eprom oe a8 a15 a0 a7 d0 d7 (instruction) ADUC816 psen p2 ale p0 figure 43. external program memory interface note that program memory addresses are always 16 bits wide, even in cases where the actual amount of program memory used is less than 64 kbytes. external program execution sacrifices two of the 8-bit ports (p0 and p2) to the function of addressing the program memory. while executing from external program memory, ports 0 and 2 can be used simultaneously for read/write access to exter- nal data memory, but not for general-purpose i/o. though both external program memory and external data memory are accessed by some of the same pins, the two are completely independent of each other from a software point of view. for example, the chip can read/write external data memory while executing from external program memory. figure 44 shows a hardware configuration for accessing up to 64 kbytes of external ram. this interface is standard to any 8051 compatible mcu. latch sram oe a8 a15 a0 a7 d0 d7 (data) ADUC816 rd p2 ale p0 we wr figure 44. external data memory interface (64 k ad dress space) if access to more than 64 kbytes of ram is desired, a feature unique to the ADUC816 allows addressing up to 16 mbytes of external ram simply by adding an additional latch as illus trated in figure 45.
rev. 0 ADUC816 C63C latch ADUC816 rd p2 ale p0 wr latch sram oe a8 a15 a0 a7 d0 d7 (data) we a16 a23 figure 45. external data memory interface (16 m bytes address space) in either implementation, port 0 (p0) serves as a multiplexed address/data bus. it emits the low byte of the data pointer (dpl) as an address, which is latched by a pulse of ale prior to data being placed on the bus by the ADUC816 (write operation) or the sram (read operation). port 2 (p2) provides the data pointer page byte (dpp) to be latched by ale, followed by the data pointer high byte (dph). if no latch is connected to p2, dpp is ignored by the sram, and the 8051 standard of 64 kbyte ex ternal data memory access is maintained. detailed timing diagrams of external program and data memory read and write access can be found in the timing specification sections of this data sheet. power-on reset operation external por (power-on reset) circuitry must be implemented to drive the reset pin of the ADUC816. the circuit must hold the reset pin asserted (high) whenever the power supply (dv dd ) is below 2.5 v. furthermore, v dd must remain above 2.5 v for at least 10 ms before the reset signal is deasserted (low) by which time the power supply must have reached at least a 2.7 v level. the external por circuit must be opera- tional down to 1.2 v or less. the timing diagram of figure 46 illustrates this functionality under three separate events: power- up, brownout, and power-down. notice that when reset is asserted (high) it tracks the voltage on dv dd . 10ms min 1.2v max 10ms min 2.5v min 1.2v max dv dd reset figure 46. external por timing the best way to implement an external por function to meet the above requirements involves the use of a dedicated por chip, such as the adm809/adm810 sot-23 packaged pors from analog devices. recommended connection diagrams for both active- high adm810 and active-low adm809 pors are shown in figure 47 and figure 48, respectively. dv dd reset 48 34 20 15 ADUC816 por (active high) power supply figure 47. external active high por circuit some active-low por chips, such as the adm 809 can be used with a manual push-button as an additional reset source as illustrated by the dashed line connection in figure 48. dv dd reset 48 34 20 ADUC816 15 optional manual reset push-button por (active low) power supply 1k figure 48. external active low por circuit power supplies the ADUC816? operational power supply voltage range is 2.7 v to 5.25 v. although the guaranteed data sheet specifications are given only for power supplies within 2.7 v to 3.6 v or +5% of the nominal 5 v level, the chip will function equally well at any power supply level between 2.7 v and 5.25 v. separate analog and digital power supply pins (av dd and dv dd respectively) allow av dd to be kept relatively free of noisy digital signals often present on the system dvdd line. in this mode the part can also operate with split supplies; that is, using different voltage supply levels for each supply. for example, this means that the system can be designed to operate with a dv dd voltage level of 3 v while the av dd level can be at 5 v or vice-versa if re quired. a typical split supply configuration is shown in figure 49. dv dd 48 34 20 ADUC816 5 6 agnd av dd + 0.1 f 10 f analog supply 10 f dgnd 35 21 47 0.1 f + digital supply figure 49. external dual supply connections
rev. 0 ADUC816 C64C as an alternative to providing two separate power supplies, av dd quiet by placing a small series resistor and/or ferrite bead between it and dv dd , and then decoupling av dd separately to ground. an example of this configuration is shown in figure 50. with this configuration other analog circuitry (such as op amps, voltage reference, etc.) can be powered from the av dd supply line as w ell. dv dd 48 34 20 ADUC816 5 6 agnd av dd 0.1 f 10 f dgnd 35 21 47 0.1 f + digital supply 10 f 1.6 bead figure 50. external single supply connections notice that in both figure 49 and figure 50, a large value (10 f) reservoir capacitor sits on dv dd and a separate 10 f capacitor sits on av dd . also, local small-value (0.1 f) capacitors are located at each vdd pin of the chip. as per standard design p rac- tice, be sure to include all of these capacitors, and ensure the smaller capacitors are closest to each av dd pin with trace lengths as short as possible. connect the ground terminal of each of these capacitors directly to the underlying ground plane. finally, it should also be noticed that, at all times, the analog and digital ground pins on the ADUC816 should be referenced to the same system ground reference point. power consumption the ?ore?values given represent the current drawn by dv dd , while the rest (?dc?and ?ac? are pulled by the av dd pin and can be disabled in software when not in use. the other on-chip peripherals (watchdog timer, power supply monitor, etc.) consume negligible current and are there fore lumped in with the ?ore?operating current here. of course, the user must add any currents sourced by the parallel and serial i/o pins, and that sourced by the dac, in order to determine the total current needed at the ADUC816? supply pins. also, current draw from the dvdd supply will increase by approximately 5 ma during flash/ee erase and program cycles power-saving modes setting the idle and power-down mode bits, pcon.0 and pcon.1 respectively, in the pcon sfr described in table ii, allows the chip to be switched from normal mode into idle mode, and also into full power-down mode. in idle mode, the oscillator continues to run, but the core clock generated from the pll is halted. the on-chip peripherals con- tinue to receive the clock, and remain functional. the cpu status is preserved with the stack pointer, program counter, and all other internal registers maintain their data during idle mode. port pins and dac output pins also retain their states, and ale and psen outputs go high in this mode. the chip will recover from idle mode upon receiving any enabled interrupt, or on receiving a hardware reset. in power-down mode, both the pll and the clock to the core are stopped. the on-chip oscillator can be halted or can con tinue to oscillate depending on the state of the oscillator power-down bit (osc_pd) in the pllcon sfr. the tic, being driven directly from the oscillator, can also be enabled during power- down. all other on-chip peripherals however, are shut down. port pins retain their logic levels in this mode, but the dac output goes to a high-impedance state (three-state) while ale and psen outputs are held low. during full power-down mode, the ADUC816 consumes a total of 5 a typically. there are five ways of terminating power-down mode: asserting the reset pin (15) returns to normal mode all registers are set to their default state and program execution starts at the reset vector once the reset pin is deasserted. cycling power all registers are set to their default state and program execution starts at the reset vector. time interval counter (tic) interrupt power-down mode is terminated and the cpu services the tic interrupt, the reti at the end of the tic interrupt service routine will return the core to the instruction after that which enabled power down. i 2 c or spi interrupt power-down mode is terminated and the cpu services the i 2 c/ spi interrupt. the reti at the end of the isr will return the core to the instruction after that which enabled power down. it should be noted that the i 2 c/spi power down interrupt enable bit (seripd) in the pcon sfr must first be set to allow this mode of operation. int0 interrupt power-down mode is terminated and the cpu services the int0 interrupt. the reti at the end of the isr will return the core to the instruction after that which enabled power-down. it should be noted that the int0 power-down interrupt enable bit (int0pd) in the pcon sfr must first be set to allow this mode of operation. grounding and board layout recommendations as with all high resolution data converters, special attention must be paid to grounding and pc board layout of ADUC816-based designs in order to achieve optimum performance from the adcs and dac. although the ADUC816 has separate pins for analog and digital ground (agnd and dgnd), the user must not tie these to two separate ground planes unless the two ground planes are con- nected together very close to the ADUC816, as illustrated in the simplified example of figure 51a. in systems where digital and analog ground planes are connected together somewhere else (at the system? power supply for example), they cannot be con- nected again near the ADUC816 since a ground loop would result. in these cases, tie the ADUC816? agnd and dgnd pins all to the analog ground plane, as illustrated in figure 51b. in systems with only one ground plane, ensure that the digital and analog components are physically separated onto separate halves of the board such that digital return currents do not flow near analog circuitry and vice versa. the ADUC816 can then be placed between the digital and analog sections, as illustrated in figure 51c.
rev. 0 ADUC816 C65C dgnd place analog components here a b c agnd dgndagnd place digital components here place analog components here place digital components here gnd place analog components here place digital components here figure 51. system grounding schemes in all of these scenarios, and in more complicated real-life appli- cations, keep in mind the flow of current from the supplies and back to ground. make sure the return paths for all currents are as close as possible to the paths the currents took to reach their destinations. for example, do not power components on the analog side of figure 51b with dv dd since that would force return currents from dv dd to flow through agnd. also, try to avoid digital currents flowing under analog circuitry, which could happen if the user placed a noisy digital chip on the left half of the board in figure 51c. whenever possible, avoid large discontinuities in the ground plane(s) (such as are formed by a long trace on the same layer), since they force return signals to travel a longer path. and of course, make all connections to the ground plane directly, with little or no trace separating the pin from its via to ground. if the user plans to connect fast logic signals (rise/fall time < 5 ns) to any of the ADUC816? digital inputs, add a series resistor to each relevant line to keep rise and fall times longer than 5 ns at the ADUC816 input pins. a value of 100 ? or 200 ? is usually sufficient to prevent high-speed signals from coupling capaci tively into the ADUC816 and affecting the accuracy of adc conver sions. ADUC816 system self-identification in some hardware designs it may be an advantage for the soft- ware running on the ADUC816 target to identify the host micro- converter. for example, code running on the ADUC816 may be used at future date to run on an ADUC816 microconverter host and the code may be required to operate differently. the chipid sfr is a read-only register located at sfr address c2 hex. the top nibble of this byte is set to ??to designate an aduc824 host. for an aduc824 host, the chipid sfr will contain the value ??in the upper nibble. other hardware considerations to facilitate in-circuit programming, plus in-circuit debug and emulation options, users will want to implement some simple connection points in their hardware that will allow easy access to download, debug, and emulation modes. in-circuit serial download access nearly all ADUC816 designs will want to take advantage of the in-circuit reprogrammability of the chip. this is accomplished by a connection to the ADUC816? uart, which requires an external rs-232 chip for level translation if downloading code from a pc. basic configuration of an rs-232 connection is illustrated in figure 52 with a simple adm202-based circuit. if users would rather not design an rs-232 chip onto a board, refer to the appli- cation note ?c006? 4-wire uart-to-pc interface 1 for a simple (and zero-cost-per-board) method of gaining in-circuit serial download access to the ADUC816. note 1 application note uc006 is available at www.analog.com/microconverter in addition to the basic uart connections, users will also need a way to trigger the chip into download mode. this is accom- plished via a 1 k ? pull-down resistor that can be jumpered onto the psen pin, as shown in figure 52. to get the ADUC816 into download mode, simply connect this jumper and power- cycle the device (or manually reset the device, if a manual reset button is available) and it will be ready to receive a new program serially. with the jumper removed, the device will come up in normal mode (and run the program) whenever power is cycled or reset is toggled. note that psen is normally an output (as described in the exter- nal memory interface section) and it is sampled as an input only on the falling edge of reset (i.e., at power-up or upon an external manual reset). note also that if any external circuitry unintentionally pulls psen low during power-up or reset events, it could cause the chip to enter download mode and therefore fail to begin user code execution as it should. to prevent this, ensure that no external signals are capable of pulling the psen pin low, except for the external psen jumper itself. embedded serial port debugger from a hardware perspective, entry to serial port debug mode is identical to the serial download entry sequence described above. in fact, both serial download and serial port debug modes can be thought of as essentially one mode of operation used in two different ways. note that the serial port debugger is fully contained on the ADUC816 device, (unlike ?om monitor?type debuggers) and therefore no external memory is needed to enable in-system debug sessions. single-pin emulation mode also built into the ADUC816 is a dedicated controller for single- pin in-circuit emulation (ice) using standard production ADUC816 devices. in this mode, emulation access is gained by connection to a single pin, the ea pin. normally, this pin is hard- wired either high or low to select execution from internal or external program memory space, as described earlier. to enable single-pin emulation mode, however, users will need to pull the ea pin high through a 1 k ? resistor as shown in figure 52. the emulator will then connect to the 2-pin header also shown in figure 52. to be compatible with the standard connector that
rev. 0 ADUC816 C66C comes with the single-pin emulator available from accutron lim ited ( www.accutron.com ), use a 2-pin 0.1-inch pitch ?riction lock header from molex ( www.molex.com ) such as their part nu m ber 22-27-2021. be sure to observe the polarity of this header. as represented in figure 52, when the friction lock tab is at the right, the ground pin should be the lower of the two pins (when viewed from the top). enhanced-hooks emulation mode ADUC816 also supports enhanced-hooks emulation mode. an enhanced-hooks-based emulator is available from metalink c orpo- ration ( www.metaice.com ). no special hardware support for these emulators needs to be designed onto the board since these are pod-style?emulators where users must replace the chip on their board with a header device that the emulator pod plugs into. the only hardware concern is then one of determining if adequate space is available for the emulator pod to fit into the system enclosure. typical system configuration a typical ADUC816 configuration is shown in figure 52. it sum- marizes some of the hardware considerations discussed in the previous paragraphs. figure 52 also includes connections for a typical analog measure- ment application of the ADUC816, namely an interface to an rtd (resistive temperature device). the arrangement shown is commonly referred to as a 4-wire rtd configuration. here, the on-chip excitation current sources are enabled to excite the sensor. an external differential reference voltage is generated by the current sourced through resistor r1. this current also flows directly through the rtd, which generates a differential voltage directly proportional to temperature. this differential voltage is routed directly to the positive and negative inputs of the primary adc (ain1, ain2 respectively). a second external resistor, r2, is used to ensure that absolute analog input voltage on the negative input to the primary adc stays within that specified for the ADUC816, i.e., agnd + 100 mv. c1+ v+ c1 c2+ c2 v t2out r2in v cc gnd t1out r1in r1out t1in t2in r2out adm202 dv dd 39 40 47 46 44 43 42 41 52 51 50 49 48 45 dv dd 1k dv dd 1k 2-pin header for emulation access (normally open) download/debug enable jumper (normally open) 32.766khz dv dd 1 9-pin d-sub female 2 3 4 5 6 7 8 9 av dd v ref + v ref a in + a in 200 a/400 a excitation current r2 510 rtd r1 5.6k av dd agnd p1.2iexc1/dac refin refin+ p1.4/ain1 p1.5/ain2 dv dd dgnd psen ea dgnd dv dd xtal2 xtal1 reset rxd txd dv dd dgnd adm810 v cc rst gnd dvdd not connected in this example dv dd ADUC816 27 34 33 31 30 29 28 38 37 36 35 32 figure 52. typical system configuration
rev. 0 ADUC816 C67C it should also be noted that variations in the excitation current do not affect the measurement system, as the input voltage from the rtd and reference voltage across r1 vary ratiometrically with the excitation current. resistor r1 must, however, have a low temperature coefficient to avoid errors in the reference volt- age over temperature. quickstart development system the quickstart development system is a full featured, low cost development tool suite supporting the ADUC816. the system consists of the following pc-based (windows-compatible) hard- ware and software development tools. hardware: ADUC816 evaluation board, plug-in power supply and serial port c able code development: 8051 assembler c compiler (2 kcode lim ited) code functionality: adsim, windows microconverter code simulator in-circuit code download: serial downloader in-circuit debugger: serial port debugger misc. other: cd-rom documentation and two additional p rototype devices figures 53 shows the typical components of a quickstart devel- opment system while figure 54 shows a typical debug session. a brief description of some of the software tools?components in the quickstart development system is given below. figure 53. components of the quickstart development system download?n-circuit serial downloader the serial downloader is a software program that allows the user to serially download an assembled program (intel hex format file) to the on-chip program flash memory via the serial com1 port on a standard pc. an application note (uc004) detailing this serial download protocol is available from www.analog.com/ microconverter. debug?n-circuit debugger the debugger is a windows application that allows the user to debug code execution on silicon using the microconverter uart serial port. the debugger provides access to all on-chip periph- erals during a typical debug session as well as single-step and break-point code execution control. adsim?indows simulator the simulator is a windows application that fully simulates all the microconverter functionality including adc and dac peripherals. the simulator provides an easy-to-use, intuitive, in ter- face to the microconverter functionality and integrates many standard debug features; including multiple breakpoints, single stepping; and code execution trace capability. this tool can be used both as a tutorial guide to the part as well as an efficient way to prove code functionality before moving to a hardware plat form. the quickstart development tool-suite software is freely available at the analog devices microconverter website www.analog.com/microconverter. figure 54. typical debug session
rev. 0 C68C c00436C2.5C2/01 (rev. 0) printed in u.s.a. ADUC816 outline dimensions dimensions shown in inches and (mm). 52-lead mqfp (s-52) top view (pins down) 1 13 14 27 26 39 40 52 pin 1 0.014 (0.35) 0.010 (0.25) 0.557 (14.15) 0.537 (13.65) 0.398 (10.11) 0.390 (9.91) 0.557 (14.15) 0.537 (13.65) 0.398 (10.11) 0.390 (9.91) 0.0256 (0.65) bsc 0.082 (2.09) 0.078 (1.97) 0.012 (0.30) 0.006 (0.15) 0.008 (0.20) 0.006 (0.15) seating plane 0.037 (0.95) 0.026 (0.65) 0.094 (2.39) 0.084 (2.13)

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